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參數(shù)資料
| 型號： | AT91SAM9N12-EK |
| 廠商： | Atmel |
| 文件頁數(shù)： | 18/27頁 |
| 文件大小： | 0K |
| 描述： | EVAL KIT FOR SAM9N12 |
| 設(shè)計資源： | AT91SAM9N12-EK Design & Mfg Files SAM9N12-EK Design & Mfg File Information |
| 標準包裝： | 1 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ATSAM9N12 |
| 所含物品： | 板 |
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11096AS–ATARM–4-Oct-11
SAM9N12
8.3
Peripheral Interrupts and Clock Control
8.3.1
System Interrupt
The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:
the DDR2/LPDDR Controller
the Debug Unit
the Periodic Interval Timer
the Real-Time Clock
the Watchdog Timer
the Reset Controller
the Power Management Controller
The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used
within the Advanced Interrupt Controller.
8.3.2
External Interrupts
All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signal IRQ, use a
dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs.
8.4
Peripheral Signal Multiplexing on I/O Lines
The SAM9N12 features 4 PIO controllers, PIOA, PIOB, PIOC and PIOD, which multiplex the I/O
lines of the peripheral set.
Each PIO Controller controls 32 lines, 19 lines, 32 lines and 22 lines respectively for PIOA, PIOB,
PIOC and PIOD. Each line can be assigned to one of three peripheral functions, A, B or C.
Refer to Section 4. “Package and Pinout” and the package pinout table, Table 4-1, depending on
the package.
8.4.1
Reset State
The column “Reset State” (Table 4-1) indicates the reset state of the line with mnemonics.
“PIO”/”signal”
Indicates whether the PIO Line resets in I/O mode or in peripheral mode. If “PIO” is mentioned,
the PIO Line is maintained in a static state as soon as the reset is released. As a result, the bit
corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low.
If a signal name is mentioned in the “Reset State” column, the PIO Line is assigned to this func-
tion and the corresponding bit in PIO_PSR resets high. This is the case on pins controlling
memories, in particular the address lines, which require the pin to be driven as soon as the reset
is released.
27
Reserved
28
SSC
Synchronous Serial Controller
29
Reserved
30
TRNG
True Random Number Generator
31
AIC
Advanced Interrupt Controller
IRQ
Table 8-1.
SAM9N12 Peripheral Identifiers (Continued)
Instance ID
Instance name
Instance description
External interrupt
Wired-or interrupt
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