參數(shù)資料
型號: AT91SAM9N12-EK
廠商: Atmel
文件頁數(shù): 1/27頁
文件大?。?/td> 0K
描述: EVAL KIT FOR SAM9N12
設計資源: AT91SAM9N12-EK Design & Mfg Files
SAM9N12-EK Design & Mfg File Information
標準包裝: 1
類型: MCU
適用于相關產(chǎn)品: ATSAM9N12
所含物品:
Features
Core
– ARM926EJ-S ARM Thumb Processor running up to 400 MHz @ 1.0V +/- 10%
– 16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit
Memories
– One 128-Kbyte internal ROM embedding bootstrap routine
– One 32-Kbyte internal SRAM, single-cycle access at system speed
32-bit External Bus Interface supporting 8-bank DDR2/LPDDR, SDR/LPSDR, Static
Memories
– MLC/SLC NAND Controller, with up to 24-bit Programmable Multi-bit Error
Correcting Code (PMECC)
System running up to 133 MHz
– Power-on Reset,
Reset Controller, Shut Down Controller, Periodic Interval Timer,
Watchdog Timer and Real Time Clock
– Boot Mode Select Option, Remap Command
– Internal Low Power 32 kHz RC and Fast 12 MHz RC Oscillators
– Selectable 32768 Hz Low-power Oscillator, 16 MHz Oscillator,
one PLL for the
system and one PLL optimized for USB
–Six
32-bit-layer AHB Bus Matrix
– Dual Peripheral Bridge with dedicated programmable clock
– One dual port 8-channel DMA Controller
– Advanced Interrupt Controller and Debug Unit
– Two Programmable External Clock Signals
Low Power Mode
– Shut Down Controller with four 32-bit battery backup registers
– Clock Generator and Power Management Controller
– Very Slow Clock Operating Mode, Software Programmable Power Optimization
Capabilities
Peripherals
– LCD Controller
– USB Device Full Speed with dedicated On-Chip Transceiver
– USB Host Full Speed with dedicated On-Chip Transceiver
– One High speed SD card and SDIO Host Controller
– Two Master/Slave Serial Peripheral Interfaces
– Two Three-channel 32-bit Timer/Counters
– One Synchronous Serial Controller
– One Four-channel 16-bit PWM Controller
– Two Two-wire Interfaces
– Four USARTs plus two UARTs
– One 12-channel 10-bit Analog-to-Digital Converter with up to 5-wire resistive
Touch screen support
Customizing
– TRNG True Random Number Generator compliant with NIST Special Publication
800-22
– 320 Fuse bits for device configuration, including JTAG disable and forced boot
from the on-chip ROM
I/O
– Four 32-bit Parallel Input/Output Controllers
– 105 Programmable I/O Lines Multiplexed with up to Three Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line, optional Schmitt Trigger input
– Individually Programmable Open-drain, Pull-up and Pull-down Resistor,
Synchronous Output
– Package: 217-ball BGA, pitch 0.8 mm
AT91SAM
ARM-based
Embedded MPU
SAM9N12
Summary
11096AS–ATARM–4-Oct-11
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