參數(shù)資料
型號(hào): 97SD3248RPMI
廠商: MAXWELL TECHNOLOGIES
元件分類: DRAM
英文描述: 32M X 48 SYNCHRONOUS DRAM, 6 ns, QFP132
封裝: STACK, QFP-132
文件頁(yè)數(shù): 24/40頁(yè)
文件大?。?/td> 758K
代理商: 97SD3248RPMI
97SD3248
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30
All data sheets are subject to change without notice
2004 Maxwell Technologies
All rights reserved.
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
03.25.04 Rev 1
2. Same bank: The consecutive write command ( the same bank) is illegal.
Read with Auto Precharge to Write command interval
1. Different bank: When some banks are in the active state, the second write command (another bank) is
executed. However, DQM must be set High so that the output buffer becomes High-Z before data input. The
internal auto-precharge of one bank starts at the next clock of the second command.
Read with Auto Precharge to Write Command Interval (Different bank)
2. Same bank: The consecutive write command from read with auto precharge ( the same bank) is illegal. It
is necessary to separate the two commands with a bank active command.
Write with Auto Precharege to Read command interval
1. Different bank: When some banks are in the active state, the second read command (another bank) is
executed. However, in the case of a burst write, data will continue to be written until one clock before the
read command is executed. The internal auto precharge of one bank starts at the next clock of the second
command.
Write with Auto Precharge to Read command Interval (Different bank)
相關(guān)PDF資料
PDF描述
97SD3248RPMK 32M X 48 SYNCHRONOUS DRAM, 6 ns, QFP132
97U870AKIT 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40
97U870AH 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52
97U870AHIT 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52
97U870AKT 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40
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