- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25548 > 97SD3248RPMI (MAXWELL TECHNOLOGIES) 32M X 48 SYNCHRONOUS DRAM, 6 ns, QFP132 PDF資料下載
參數(shù)資料
| 型號： | 97SD3248RPMI |
| 廠商： | MAXWELL TECHNOLOGIES |
| 元件分類： | DRAM |
| 英文描述： | 32M X 48 SYNCHRONOUS DRAM, 6 ns, QFP132 |
| 封裝： | STACK, QFP-132 |
| 文件頁數(shù)： | 2/40頁 |
| 文件大?。?/td> | 758K |
| 代理商： | 97SD3248RPMI |
第1頁當(dāng)前第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
97SD3248
M
em
o
ry
10
All data sheets are subject to change without notice
2004 Maxwell Technologies
All rights reserved.
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
03.25.04 Rev 1
DQM Truth Table
Note: H: V
IH L: VIL x VIH or VIL
Write: I
DID is Needed
Read: I
DOD is Needed
The SDRAM can mask input/output data by means of DQM.
During reading, the output buffer is set to Low-Z by setting DQM to Low, enabling data output. On the other
hand, when DQM is set High, the output buffer becomes High-Z, disabling data output.
During writing, data is written by setting DQM to Low. When DQM is set to High, the previous data is held
( the new data is not written). Desired data can be masked during burst read or burst write by setting DQM..
For more details, refer to the DQM control section of the SDRAM operating instructions.
CKE Truth Table
Note: H:V
IH L:VIL x VIH or VIL
COMMAND
SYMBOL
CKE = N-1
CKE = N
DQM
Byte (DQ0 to DQ47) write enable/output
enable
ENB
H
x
L
Byte (DQ0 to DQ47) write inhibit/output dis-
able
MASK
H
x
H
CURRENT STATE
COMMAND
N
-1
N
CS
RAS
CAS
WE
ADDRESS
Active
Clock suspended mode entry
H
L
x
Any
Clock Suspend
L
x
Clock Suspend
Clock Suspend mode exit
L
H
x
Idle
Auto-refresh command (REF)
H
L
H
x
Idle
Self-refresh entry (SELF)
H
L
H
x
Idle
Power down entry
HL
LH
H
x
H
L
HL
xxx
x
Self Refresh
Self Refresh exit (SELFX)
L
H
L
H
x
Power down
Power down exit
LH
H
x
L
H
xxx
x
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 97SD3248RPMK | 32M X 48 SYNCHRONOUS DRAM, 6 ns, QFP132 |
| 97U870AKIT | 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40 |
| 97U870AH | 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 97U870AHIT | 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 97U870AKT | 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 97SD3248RPQE | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks |
| 97SD3248RPQH | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks |
| 97SD3248RPQI | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks |
| 97SD3248RPQK | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks |
| 97SG-1 | 制造商:EECO Switch 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。