參數(shù)資料
型號: AT91RM9200-QI-002 SL383
廠商: Atmel
文件頁數(shù): 5/41頁
文件大?。?/td> 0K
描述: IC ARM MCU 16BIT 128K 208PQFP
標(biāo)準(zhǔn)包裝: 200
系列: AT91
核心處理器: ARM9
芯體尺寸: 16/32-位
速度: 180MHz
連通性: EBI/EMI,以太網(wǎng),I²C,MMC,SPI,SSC,UART/USART,USB
外圍設(shè)備: POR
輸入/輸出數(shù): 122
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: ROM
RAM 容量: 48K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 208-MQFP,208-PQFP
包裝: 帶卷 (TR)
其它名稱: AT91RM9200QI002SL
13
1768MS–ATARM–09-Jul-09
AT91RM9200
5.
Power Considerations
5.1
Power Supplies
The AT91RM9200 has five types of power supply pins:
VDDCORE pins. They power the core, including processor, memories and peripherals;
voltage ranges from 1.65V to 1.95V, 1.8V nominal.
VDDIOM pins. They power the External Bus Interface I/O lines; voltage ranges from 3.0V to
3.6V, 3V or 3.3V nominal.
VDDIOP pins. They power the Peripheral I/O lines and the USB transceivers; voltage ranges
from 3.0V to 3.6V, 3V or 3.3V nominal.
VDDPLL pins. They power the PLL cells; voltage ranges from 1.65V to 1.95V, 1.8V nominal.
VDDOSC pin. They power both oscillators; voltage ranges from 1.65V to 1.95V, 1.8V
nominal.
The double power supplies VDDIOM and VDDIOP are identified in Table 4-1 on page 9 and
Table 4-2 on page 11. These supplies enable the user to power the device differently for inter-
facing with memories and for interfacing with peripherals.
Ground pins are common to all power supplies, except VDDPLL and VDDOSC pins. For these
pins, GNDPLL and GNDOSC are provided, respectively.
5.2
Power Consumption
The AT91RM9200 consumes about 500 A of static current on VDDCORE at 25
C. For
dynamic power consumption, the AT91RM9200 consumes a maximum of 25 mA on VDDCORE
at maximum speed in typical conditions (1.8V, 25
C), processor running full-performance
algorithm.
6.
I/O Considerations
6.1
JTAG Port Pins
TMS and TDI are Schmitt trigger inputs and integrate internal pull-up resistors of 15 kOhm typi-
cal. TCK is a Schmitt trigger input without internal pull-up resistor.
TDO is a tri-state output. The JTAGSEL pin is used to select the JTAG boundary scan when
asserted at a high level. The NTRST pin is used to initialize the EmbeddedICE
TAP Controller.
6.2
Test Pin
The TST0 and TST1 pins are used for manufacturing test purposes when asserted high. As they
do not integrate a pull-down resistor, they must be tied low during normal operations. Driving this
line at a high level leads to unpredictable results.
6.3
Reset Pin
NRST is a Schmitt trigger without pull-up resistor. The NRST signal is inserted in the Boundary
Scan.
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