參數(shù)資料
型號: AT90S8515-8PC
廠商: Atmel
文件頁數(shù): 98/112頁
文件大?。?/td> 0K
描述: IC MCU 8K FLSH 8MHZ 40DIP
標(biāo)準(zhǔn)包裝: 18
系列: AVR® 90S
核心處理器: AVR
芯體尺寸: 8-位
速度: 8MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 8KB(4K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
86
AT90S8515
0841G–09/01
Serial Downloading
Both the program and data memory arrays can be programmed using the SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and
MISO (output). See Figure 64. After RESET is set low, the Programming Enable instruc-
tion needs to be executed first before program/erase instructions can be executed.
Figure 64. Serial Programming and Verify
For the EEPROM, an auto-erase cycle is provided within the self-timed Write instruction
and there is no need to first execute the Chip Erase instruction. The Chip Erase instruc-
tion turns the content of every memory location in both the program and EEPROM
arrays into $FF.
The program and EEPROM memory arrays have separate address spaces: $0000 to
$0FFF (AT90S8515) for program memory and $0000 to $01FF (AT90S8515) for
EEPROM memory.
Either an external clock is supplied at pin XTAL1 or a crystal needs to be connected
across pins XTAL1 and XTAL2. The minimum low and high periods for the serial clock
(SCK) input are defined as follows:
Low: > 2 XTAL1 clock cycles
High: > 2 XTAL1 clock cycles
Serial Programming
Algorithm
When writing serial data to the AT90S8515, data is clocked on the rising edge of SCK.
When reading data from the AT90S8515, data is clocked on the falling edge of SCK.
To program and verify the AT90S8515 in the Serial Programming Mode, the following
sequence is recommended (see 4-byte instruction formats in Table 32
):
1.
Power-up sequence:
Apply power between V
CC and GND while RESET and SCK are set to “0”. If a crys-
tal is not connected across pins XTAL1 and XTAL2, apply a clock signal to the
XTAL1 pin. In some systems, the programmer cannot guarantee that SCK is held
low during power-up. In this case, RESET must be given a positive pulse of at least
two XTAL1 cycles duration after SCK has been set to “0”.
2.
Wait for at least 20 ms and enable serial programming by sending the Program-
ming Enable serial instruction to the MOSI (PB5) pin.
3.
The serial programming instructions will not work if the communication is out of
synchronization. When in sync, the second byte ($53) will echo back when issu-
VCC
2.7 - 6.0V
PB7
PB6
PB5
RESET
GND
XTAL1
SCK
MISO
MOSI
GND
CLOCK INPUT
AT90S8515
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