MCU Control Register – MCUCR The MCU Control Register contains general mic" />
參數(shù)資料
型號： AT90S1200A-4SC
廠商： Atmel
文件頁數(shù)： 10/71頁
文件大?。?/td> 0K
描述： MCU 1K FLASH 4MHZ LV 20-SOIC
標準包裝： 37
系列： AVR® 90S
核心處理器： AVR
芯體尺寸： 8-位
速度： 4MHz
連通性： SPI
外圍設備： POR，WDT
輸入/輸出數(shù)： 15
程序存儲器容量： 1KB（512 x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 64 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 6 V
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
包裝： 管件
18
AT90S1200
0838H–AVR–03/02
MCU Control Register –
MCUCR
The MCU Control Register contains general microcontroller control bits for general MCU
control functions.
Bits 7, 6 – Res: Reserved Bits
These bits are reserved bits in the AT90S1200 and always read as zero.
Bit 5 – SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the Sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the Sleep mode unless it is the pro-
grammers purpose, it is recommended to set the Sleep Enable SE bit just before the
execution of the SLEEP instruction.
Bit 4 – SM: Sleep Mode
This bit selects between the two available sleep modes. When SM is cleared (zero), Idle
mode is selected as sleep mode. When SM is set (one), Power-down mode is selected
as sleep mode. For details, refer to the paragraph “Sleep Modes” on the following page.
Bits 3, 2 – Res: Reserved Bits
These bits are reserved bits in the AT90S1200 and always read as zero.
Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the
corresponding interrupt mask in the GIMSK register is set. The level and edges on the
external INT0 pin that activate the interrupt are defined in Table 4.
The value on the INT0 pin is sampled before detecting edges. If edge interrupt is
selected, pulses with a duration longer than one CPU clock period will generate an inter-
rupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an
interrupt request as long as the pin is held low.
Bit
765
432
10
$35
––
SE
SM
––
ISC01
ISC00
MCUCR
Read/Write
R
R/W
R
R/W
Initial Value
0
Table 4. Interrupt 0 Sense Control
ISC01
ISC00
Description
0
The low level of INT0 generates an interrupt request.
01
Reserved
1
0
The falling edge of INT0 generates an interrupt request.
1
The rising edge of INT0 generates an interrupt request.
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