- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨�(m菐i)璩�(m脿i)IC缍�(w菐ng) > PDF鐩寗11795 > AT89C51ID2-SLRUM (Atmel)IC 8051 MCU 64K FLASH 44-PLCC PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | AT89C51ID2-SLRUM |
| 寤犲晢锛� | Atmel |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 48/157闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC 8051 MCU 64K FLASH 44-PLCC |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | MCU Product Line Introduction |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 500 |
| 绯诲垪锛� | 89C |
| 鏍稿績铏曠悊鍣細 | 8051 |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 60MHz |
| 閫ｉ€氭€э細 | I²C锛孲PI锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | POR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 34 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 64KB锛�64K x 8锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | 闁冨瓨 |
| EEPROM 澶�?銆�?/td> | 2K x 8 |
| RAM 瀹归噺锛� | 2K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.7 V ~ 5.5 V |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 44-LCC锛圝 褰㈠紩绶氾級 |
| 鍖呰锛� | 妯�(bi膩o)婧�(zh菙n)鍖呰 |
| 鍏跺畠鍚嶇ū锛� | AT89C51ID2-SLRUMDKR |
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141
AT89C51ID2
4289C鈥�8051鈥�11/05
Notes:
1. Operating I
CC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 60), VIL =
VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used
(see Figure 57).
2. Idle I
CC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V, VIH = VCC -
3. Power-down ICC is measured with all output pins disconnected; EA = VCC, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Fig-
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operation. In the worst cases (capacitive loading 100 pF), the noise pulse on the ALE line may exceed
0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typical values are based on a limited number of samples and are not guaranteed. The values listed are at room temperature
and 5V.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum I
OL per 8-bit port:
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total I
OL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
V
OH1
Output High Voltage, port 0, ALE, PSEN
V
CC - 0.3
V
CC - 0.7
V
CC - 1.5
V
CC = 5V 卤 10%
I
OH = -200 渭A
I
OH = -3.2 mA
I
OH = -7.0 mA
0.9 V
CC
V
CC = 2.7V to 5.5V
I
OH = -10 渭A
R
RST
RST Pull-down Resistor
50
200(5)
250
k
惟
I
IL
Logical 0 Input Current ports 1, 2, 3, 4 and 5
-50
渭AV
IN = 0.45V
I
LI
Input Leakage Current
卤10
渭A
0.45V < V
IN < VCC
I
TL
Logical 1 to 0 Transition Current, ports 1, 2, 3, 4
-650
渭AV
IN = 2.0V
C
IO
Capacitance of I/O Buffer
10
pF
F
C = 3 MHz
T
A = 25掳C
I
PD
Power-down Current
75
150
渭A
2.7 < V
CC < 5.5V
(3)
I
CCOP
Power Supply Current on normal mode
0.4 x Frequency (MHz) + 5
mA
V
CC = 5.5V
(1)
I
CCIDLE
Power Supply Current on idle mode
0.3 x Frequency (MHz) + 5
mA
V
CC = 5.5V
(2)
I
CCWRITE
Power Supply Current on flash or EEdata write
0.8 x Frequency (MHz) + 15
mA
V
CC = 5.5V
t
WRITE
Flash or EEdata programming time
7
10
ms
2.7 < V
CC < 5.5V
T
A = -40掳C to +85掳C; VSS = 0V;
V
CC =2.7V to 5.5V and F = 0 to 40 MHz (both internal and external code execution)
V
CC =4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only) (Continued)
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
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