參數(shù)資料
型號: AT89C51ID2-SLRUM
廠商: Atmel
文件頁數(shù): 23/157頁
文件大?。?/td> 0K
描述: IC 8051 MCU 64K FLASH 44-PLCC
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標(biāo)準(zhǔn)包裝: 500
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 60MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: AT89C51ID2-SLRUMDKR
119
AT89C51ID2
4289C–8051–11/05
Table 90. Default Values
After programming the part by ISP, the BSB must be cleared (00h) in order to allow the
application to boot at 0000h.
The content of the Software Security Byte (SSB) is described in Table 90 and Table 93.
To assure code protection from a parallel access, the HSB must also be at the required
level.
Table 91. Software Security Byte
The two lock bits provide different levels of protection for the on-chip code and data,
when programmed as shown to Table 93.
Mnemonic
Definition
Default value
Description
SBV
Software Boot Vector
FCh
HSB
Copy of the Hardware security byte
101x 1011b
BSB
Boot Status Byte
0FFh
SSB
Software Security Byte
FFh
Copy of the Manufacturer Code
58h
ATMEL
Copy of the Device ID #1: Family Code
D7h
C51 X2, Electrically Erasable
Copy of the Device ID #2: memories size
and type
ECh
AT89C51ID2 64KB
Copy of the Device ID #3: name and
revision
EFh
AT89C51ID2 64KB, Revision
0
Table 92.
76
543
210
--
----
LB1
LB0
Bit
Number
Bit
Mnemonic
Description
7-
Reserved
Do not clear this bit.
6-
Reserved
Do not clear this bit.
5-
Reserved
Do not clear this bit.
4-
Reserved
Do not clear this bit.
3-
Reserved
Do not clear this bit.
2-
Reserved
Do not clear this bit.
1-0
LB1-0
User Memory Lock Bits
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