參數(shù)資料
型號: AT89C5131A-PUTIM
廠商: Atmel
文件頁數(shù): 109/176頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 32K USB 32QFN
標準包裝: 260
系列: AT89C513x
核心處理器: C52X2
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,SPI,UART/USART,USB
外圍設備: LED,POR,PWM,WDT
輸入/輸出數(shù): 18
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-VQFN 裸露焊盤
包裝: 托盤
配用: AT89STK-10-ND - KIT EVAL APPL MASS STORAGE
AT89STK-05-ND - KIT STARTER FOR AT89C5131
37
AT89C5131
4136C–USB–04/05
Table 38. Program Lock bits
Notes:
1. U: unprogrammed or “one” level.
2. P: programmed or “zero” level.
3. X: don’t care
4. WARNING: Security level 2 and 3 should only be programmed after Flash and code
verification.
These security bits protect the code access through the parallel programming interface.
They are set by default to level 4. The code access through the ISP is still possible and
is controlled by the “software security bits” which are stored in the extra Flash memory
accessed by the ISP firmware.
To load a new application with the parallel programmer, a chip erase must be done first.
This will set the HSB in its inactive state and will erase the Flash memory. The part ref-
erence can always be read using Flash parallel programming modes.
Default Values
The default value of the HSB provides parts ready to be programmed with ISP:
BLJB: Cleared to force ISP operation.
X2: Set to force X1 mode (Standard Mode)
OSCON1-0: Set to start with 32 MHz oscillator configuration value.
LB2-0: Security level four to protect the code from a parallel access with maximum
security.
Software Registers
Several registers are used, in factory and by parallel programmers, to make copies of
hardware registers contents. These values are used by Atmel ISP (see Section “In-Sys-
tem Programming (ISP)”).
These registers are in the “Extra Flash Memory” part of the Flash memory. This block is
also called ”XAF” or eXtra Array Flash. They are accessed in the following ways:
Commands issued by the parallel memory programmer.
Commands issued by the ISP software.
Calls of API issued by the application software.
Several software registers are described in Table 39.
Program Lock Bits
Protection Description
Security level
LB0
LB1
LB2
1
U
No program lock features enabled.
2P
U
MOVC instruction executed from external
program memory is disabled from fetching code
bytes from any internal memory, EA is sampled
and latched on reset, and further parallel
programming of the Flash and of the EEPROM
(boot and Xdata) is disabled. ISP and software
programming with API are still allowed.
3X
P
U
Same as 2, also verify through parallel
programming interface is disabled and serial
programming ISP is disabled.
4
X
P
Same as 3, also external execution is disabled.
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