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參數(shù)資料
| 型號： | AT80C51RD2-SLSUM |
| 廠商： | Atmel |
| 文件頁數(shù)： | 81/81頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 8051 MCU 5V SPI 20MHZ 44-PLCC |
| 標(biāo)準(zhǔn)包裝： | 972 |
| 系列： | 80C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-PLCC |
| 包裝： | 管件 |
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9
4113D–8051–01/09
AT80C51RD2
6.
Enhanced Features
In comparison to the original 80C52, the microcontrollers implement the following new features:
X2 option
Dual Data Pointer
Extended RAM
Programmable Counter Array (PCA)
Hardware Watchdog
4-level Interrupt Priority System
Power-off Flag
Power On Reset
ONCE mode
ALE disabling
Some enhanced features are also located in the UART and the Timer 2
6.1
X2 Feature and OSC Clock Generation
The microcontroller core needs only 6 clock periods per machine cycle. This feature called ”X2”
provides the following advantages:
Divides frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
Saves power consumption while keeping same CPU power (oscillator power saving).
Saves power consumption by dividing dynamically the operating frequency by 2 in operating
and idle modes.
Increases CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 sig-
nal and the main clock input of the core (phase generator). This divider may be disabled by
software.
6.1.1
Description
The clock for the whole circuit and peripherals is first divided by two before being used by the
CPU core and the peripherals.
This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is
bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%.
Figure 6-1 shows the clock generation block diagram. X2 bit is validated on the rising edge of
the XTAL1
÷ 2 to avoid glitches when switching from X2 to standard mode. Figure 6-2 shows the
switching mode waveforms.
Figure 6-1.
Clock Generation Diagram
XTAL1
2
CKCON0
X2
8-bit Prescaler
F
OSC
F
XTAL
0
1
XTAL1:2
CKRL
CLK Periph
CLK CPU
Idle
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