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| 型號： | AT80C51RD2-SLSUM |
| 廠商： | Atmel |
| 文件頁數(shù)： | 7/81頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 8051 MCU 5V SPI 20MHZ 44-PLCC |
| 標(biāo)準(zhǔn)包裝： | 972 |
| 系列： | 80C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-PLCC |
| 包裝： | 管件 |
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15
4113D–8051–01/09
AT80C51RD2
Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For
example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte at address
0A0h, rather than P2 (whose address is 0A0h).
The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and
MOVX instructions. This part of memory which is physically located on-chip, logically
occupies the first bytes of external data memory. The bits XRS0 and XRS1 are used to hide a
part of the available XRAM as explained in Table 8-1. This can be useful if external
peripherals are mapped at addresses already used by the internal XRAM.
With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in
combination with any of the registers R0, R1 of the selected bank or DPTR. An access to
XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For example, with EXTRAM =
0, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at address 0A0H
rather than external memory. An access to external data memory locations higher than the
accessible size of the XRAM will be performed with the MOVX DPTR instructions in the same
way as in the standard 80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7
as write and read timing signals. Accesses to XRAM above 0FFH can only be done by the
use of DPTR.
With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51.
MOVX @ Ri will provide an eight-bit address multiplexed with data on Port 0 and any output
port pins can be used to output higher order address bits. This is to provide the external
paging capability. MOVX @DPTR will generate a sixteen-bit address. Port2 outputs the high-
order eight address bits (the contents of DPH) while Port0 multiplexes the low-order eight
address bits (DPL) with data. MOVX @ Ri and MOVX @DPTR will generate either read or
write signals on P3.6 (WR) and P3.7 (RD).
The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM)
internal data memory. The stack may not be located in the XRAM.
The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses are
extended from 6 to 30 clock periods. This is useful to access external slow peripherals.
Table 8-2.
AUXR Register
AUXR - Auxiliary Register (8Eh)
765
4321
0
-
M0
-
XRS1
XRS0
EXTRAM
AO
Bit
Number
Bit
Mnemonic
Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit
5M0
Pulse length
Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock periods
(default).
Set to stretch MOVX control: the RD and the WR pulse length is 30 clock periods.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit
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