參數(shù)資料
型號(hào)： AT6005A-4AI
廠商： Atmel
文件頁(yè)數(shù)： 27/28頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 15K GATE 4NS 144TQFP
標(biāo)準(zhǔn)包裝： 90
系列： AT6000(LV)
邏輯元件/單元數(shù)： 3136
輸入/輸出數(shù)： 108
門數(shù)： 15000
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 144-TQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
其它名稱： AT6005A4AI
AT6000(LV) Series
8
Figure 11. A-type I/O Logic
Figure 12. B-type I/O Logic
TTL/CMOS Inputs
A user-configurable bit determines the threshold level –
TTL or CMOS – of the input buffer.
Open Collector/Tristate Outputs
A user-configurable bit which enables or disables the active
pull-up of the output device.
Slew Rate Control
A user-configurable bit controls the slew rate – fast or slow
– of the output buffer. A slow slew rate, which reduces
noise and ground bounce, is recommended for outputs that
are not speed-critical. Fast and slow slew rates have the
same DC-current sinking capabilities, but the rate at which
each allows the output devices to reach full drive differs.
Pull-up
A user-configurable bit controls the pull-up transistor in the
I/O pin. It’s primary function is to provide a logical “1” to
unused input pins. When on, it is approximately equivalent
to a 25K resistor to V
CC.
Enable Select
User-configurable bits determine the output-enable for the
output driver. The output driver can be static – always on or
always off – or dynamically controlled by a signal gener-
ated in the array. Four options are available from the array:
(1) the control is low and always driving; (2) the control is
high and never driving; (3) the control is connected to a ver-
tical local bus associated with the output cell; or (4) the
control is connected to a horizontal local bus associated
with the output cell. On power-up, the user I/Os are config-
ured as inputs with pull-up resistors.
In addition to the functionality provided by the I/O logic, the
entrance and exit cells provide the ability to register both
inputs and outputs. Also, these perimeter cells (unlike inte-
rior cells) are connected directly to express buses: the
edge-facing A and B outputs of the entrance cell are con-
nected to express buses, as are the edge-facing A and B
inputs of the exit cell. These buses are perpendicular to the
edge, and provide a rapid means of bringing I/O signals to
and from the array interior and the opposite edge of the
chip.
Chip Configuration
The Integrated Development System generates the SRAM
bit pattern required to configure a AT6000 Series device. A
PC parallel port, microprocessor, EPROM or serial configu-
ration memory can be used to download configuration
patterns.
Users select from several configuration modes. Many fac-
tors, including board area, configuration speed and the
number of designs implemented in parallel can influence
the user’s final choice.
Configuration is controlled by dedicated configuration pins
and dual-function pins that double as I/O pins when the
device is in operation. The number of dual-function pins
required for each mode varies.
相關(guān)PDF資料
PDF描述
AT6005A-4AC IC FPGA 15K GATE 4NS 144TQFP
AT6005A-2AI IC FPGA 2NS 144TQFP
AT6005A-2AC IC FPGA 15K GATE 2NS 144TQFP
AT6005-4QI IC FPGA 15K GATE 4NS 132BQFP
AT6005-4QC IC FPGA 15K GATE 4NS 132BQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AT6005A-4QC 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Coprocessor Field Programmable Gate Arrays
AT6005A-4QI 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Coprocessor Field Programmable Gate Arrays
AT6005ALV-4AC 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Coprocessor Field Programmable Gate Arrays
AT6005ALV-4QC 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Coprocessor Field Programmable Gate Arrays
AT6005LV-4AC 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Coprocessor Field Programmable Gate Arrays
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*