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參數(shù)資料
| 型號： | AT6000LVSERIES |
| 英文描述： | Coprocessor Field Programmable Gate Arrays |
| 中文描述： | 協(xié)處理器現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 9/23頁 |
| 文件大?。?/td> | 591K |
| 代理商： | AT6000LVSERIES |
AC Timing Characteristics – 3.3V Operation
Delays are based on fixed load. Loads for each type of device are described in the notes. Delays are in nanoseconds.
Worst case: Vcc = 3.0V to 3.6V. Temperature = 0°C to 70°C.
Cell Function
Parameter
From
To
Load Definition
- 4
Units
Wire (4)
tPD (max) (4)
A, B, L
A, B
1
1.8
ns
NAND
tPD (max)
A, B, L
B
1
3.2
ns
XOR
tPD (max)
A, B, L
A
1
4.0
ns
AND
tPD (max)
A, B, L
B
1
3.2
ns
MUX
tPD (max)
A, B
A
1
4.0
ns
LA
1
4.9
ns
D-Flip-Flop (5)
tsetup (min)
A, B, L
CLK
3.0
ns
D-Flip-Flop (5)
thold (min)
CLK
A, B, L
0.0
ns
D-Flip-Flop
tPD (max)
CLK
A
1
3.0
ns
Bus Driver
tPD (max)
A
L
2
4.0
ns
Repeater
tPD (max)
L, E
E
3
2.3
ns
L, E
L
2
3.0
ns
Column Clock
tPD (max)
GCLK, A, ES
CLK
3
3.0
ns
Column Reset
tPD (max)
GRES, A, EN
RES
3
3.0
ns
Clock Buffer (5)
tPD (max)
CLOCK PIN
GCLK
4
2.9
ns
Reset Buffer (5)
tPD (max)
RESET PIN
GRES
5
2.8
ns
TTL Input (1)
tPD (max)
I/O
A
3
1.5
ns
CMOS Input (2)
tPD (max)
I/O
A
3
2.3
ns
Fast Output (3)
tPD (max)
A
I/O PIN
6
6.0
ns
Slow Output (3)
tPD (max)
A
I/O PIN
6
12.0
ns
Output Disable (5)
tPXZ (max)
L
I/O PIN
6
5.5
ns
Fast Enable (3, 5)
tPZX (max)
L
I/O PIN
6
6.5
ns
Slow Enable (3, 5)
tPZX (max)
L
I/O PIN
6
12.5
ns
Device
Cell Types
Outputs
Icc (max)
Cell (6)
Wire, XWire, Half-Adder, Flip-Flop
A, B
2.3
A/MHz
Bus (6)
Wire, XWire, Half-Adder, Flip-Flop, Repeater
L
1.3
A/MHz
Column Clock (6)
Column Clock Driver
CLK
20
A/MHz
Notes:
1. TTL buffer delays are measured from a VIH of 1.5V at the
pad to the internal VIH at A. The input buffer load is constant.
2. CMOS buffer delays are measured from a VIH of 1/2 VCC at
the pad to the internal VIH at A. The input buffer load is con-
stant.
3. Buffer delay is to a pad voltage of 1.5V with one output
switching.
4. Max specifications are the average of max tPDLH and tPDHL.
5. Parameter based on characterization and simulation; not
tested in production.
6. Exact power calculation is available in an Atmel application
note.
Load Definition:
1. Load of one A or B input
2. Load of one L input
3. Constant Load
4. Load of 28 Clock Columns
5. Load of 28 Reset Columns
6. Tester Load of 50 pF
AT6000/LV Series
2-19
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| AT6002-2AC | 功能描述:FPGA - 現(xiàn)場可編程門陣列 6K GATE 2NS RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| AT6002-2AI | 功能描述:FPGA - 現(xiàn)場可編程門陣列 6K GATE 2NS IND TEMP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| AT6002-2JC | 功能描述:FPGA - 現(xiàn)場可編程門陣列 6K GATE 2NS 84 RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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