參數(shù)資料
型號： AT6000LVSERIES
英文描述： Coprocessor Field Programmable Gate Arrays
中文描述： 協(xié)處理器現(xiàn)場可編程門陣列
文件頁數(shù)： 8/23頁
文件大?。?/td> 591K
代理商： AT6000LVSERIES
AC Timing Characteristics – 5V Operation
Delays are based on fixed load. Loads for each type of device are described in the notes. Delays are in nanoseconds.
Worst case: Vcc = 4.75V to 5.25V. Temperature = 0°C to 70°C.
Cell Function
Parameter
From
To
Load
Definition
- 1
- 2
- 4
Units
Wire (4)
tPD (max) (4)
A, B, L
A, B
1
0.8
1.2
1.8
ns
NAND
tPD (max)
A, B, L
B
1
1.6
2.2
3.2
ns
XOR
tPD (max)
A, B, L
A
1
1.8
2.4
4.0
ns
AND
tPD (max)
A, B, L
B
1
1.7
2.2
3.2
ns
MUX
tPD (max)
A, B
A
1
1.7
2.3
4.0
ns
L
A
1
2.1
3.0
4.9
ns
D-Flip-Flop (5)
tsetup (min)
A, B, L
CLK
1.5
2.0
3.0
ns
D-Flip-Flop (5)
thold (min)
CLK
A, B, L
0.0
ns
D-Flip-Flop
tPD (max)
CLK
A
1
1.5
2.0
3.0
ns
Bus Driver
tPD (max)
A
L
2
2.0
2.6
4.0
ns
Repeater
tPD (max)
L, E
E
3
1.3
1.6
2.3
ns
L, E
L
2
1.7
2.1
3.0
ns
Column Clock
tPD (max)
GCLK, A, ES
CLK
3
1.8
2.4
3.0
ns
Column Reset
tPD (max)
GRES, A, EN
RES
3
1.8
2.4
3.0
ns
Clock Buffer (5)
tPD (max)
CLOCK PIN
GCLK
1.6
2.0
2.9
ns
Reset Buffer (5)
tPD (max)
RESET PIN
GRES
1.5
1.9
2.8
ns
TTL Input (1)
tPD (max)
I/O
A
3
1.0
1.2
1.5
ns
CMOS Input (2)
tPD (max)
I/O
A
3
1.3
1.4
2.3
ns
Fast Output (3)
tPD (max)
A
I/O PIN
4
3.3
3.5
6.0
ns
Slow Output (3)
tPD (max)
A
I/O PIN
4
7.5
8.0
12.0
ns
Output Disable (5)
tPXZ (max)
L
I/O PIN
4
3.1
3.3
5.5
ns
Fast Enable (3, 5)
tPZX (max)
L
I/O PIN
4
3.8
4.0
6.5
ns
Slow Enable (3, 5)
tPZX (max)
L
I/O PIN
4
8.2
8.5
12.5
ns
Notes:
1. TTL buffer delays are measured from a VIH
of 1.5V at the pad to the internal VIH at A.
The input buffer load is constant.
2. CMOS buffer delays are measured from a
VIH of 1/2 VCC at the pad to the internal
VIH at A. The input buffer load is constant.
3. Buffer delay is to a pad voltage of 1.5V
with one output switching.
4. Max specifications are the average of max
tPDLH and tPDHL.
5. Parameter based on characterization and
simulation; not tested in production.
6. Exact power calculation is available in an
Atmel application note.
Load Definition:
1. Load of one A or B input
2. Load of one L input
3. Constant Load
4. Tester Load of 50 pF
Device
Cell Types
Outputs
Icc (max)
Cell (6)
Wire, XWire, Half-Adder, Flip-Flop
A, B
4.5
A/MHz
Bus (6)
Wire, XWire, Half-Adder, Flip-Flop, Repeater
L
2.5
A/MHz
Column Clock (6)
Column Clock Driver
CLK
40
A/MHz
= Preliminary Information
2-18
AT6000/LV Series
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PDF描述
AT6000SERIES Coprocessor Field Programmable Gate Arrays
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AT6000SERIES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Coprocessor Field Programmable Gate Arrays
AT6002 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Coprocessor Field Programmable Gate Arrays
AT6002-2AC 功能描述:FPGA - 現(xiàn)場可編程門陣列 6K GATE 2NS RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
AT6002-2AI 功能描述:FPGA - 現(xiàn)場可編程門陣列 6K GATE 2NS IND TEMP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
AT6002-2JC 功能描述:FPGA - 現(xiàn)場可編程門陣列 6K GATE 2NS 84 RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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