參數(shù)資料
型號: AT45BR3214B-C1
廠商: ATMEL CORP
元件分類: 存儲器
英文描述: 32-MEGABIT DATAFLASH + 4-MEGABIT SRAM STACK MEMORY
中文描述: SPECIALTY MEMORY CIRCUIT, PBGA62
封裝: 12 X 8 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, PLASTIC, CBGA-62
文件頁數(shù): 4/40頁
文件大?。?/td> 488K
代理商: AT45BR3214B-C1
4
AT45BR3214B
3356B–DFLASH–10/04
32-Mbit DataFlash
Description
The 32-Mbit DataFlash is a 2.7-volt only, serial interface Flash memory ideally suited for
a wide variety of digital voice-, image-, program code- and data-storage applications.
Its 34,603,008 bits of memory are organized as 8192 pages of 528 bytes each. In addi-
tion to the main memory, the 32-Mbit DataFlash also contains two SRAM data buffers of
528 bytes each. The buffers allow receiving of data while a page in the main memory is
being reprogrammed, as well as reading or writing a continuous data-stream. EEPROM
emulation (bit or byte alterability) is easily handled with a self-contained three step
Read-Modify-Write operation. Unlike conventional Flash memories that are accessed
randomly with multiple address lines and a parallel interface, the DataFlash uses a SPI
serial interface to sequentially access its data. DataFlash supports SPI mode 0 and
mode 3. The simple serial interface facilitates hardware layout, increases system reli-
ability, minimizes switching noise, and reduces package size and active pin count. The
device is optimized for use in many commercial and industrial applications where high
density, low pin count, low voltage, and low power are essential. The device operates at
clock frequencies up to 20 MHz with a typical active read current consumption of 4 mA.
To allow for simple in-system reprogrammability, the 32-Mbit DataFlash does not
require high input voltages for programming. The device operates from a single power
supply, 2.7V to 3.3V, for both the program and read operations. The 32-Mbit DataFlash
is enabled through the chip select pin (CS) and accessed via a three-wire interface con-
sisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK).
All programming cycles are self-timed, and no separate erase cycle is required before
programming. When the device is shipped from Atmel, the most significant page of the
memory array may not be erased. In other words, the contents of the last page may not
be filled with FFH.
DataFlash
Block Diagram
Memory Array
To provide optimal flexibility, the memory array of the 32-Mbit DataFlash is divided into
three levels of granularity comprising of sectors, blocks, and pages. The Memory Archi-
tecture Diagram illustrates the breakdown of each level and details the number of pages
per sector and block. All program operations to the DataFlash occur on a page-by-page
basis; however, the optional erase operations can be performed at the block or page
level.
FLASH MEMORY ARRAY
PAGE (528 BYTES)
BUFFER 2 (528 BYTES)
BUFFER 1 (528 BYTES)
I/O INTERFACE
SCK
CS
RESET
VCC
GND
RDY/BUSY
WP
SO
SI
相關PDF資料
PDF描述
AT45CS1282 128-megabit 2.7-volt Dual-interface Code Shadow DataFlash
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AT45D011-JI 1-Megabit 5.0-volt Only Serial DataFlash
AT45D011-SC 1-Megabit 5.0-volt Only Serial DataFlash
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