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參數(shù)資料

型號(hào)：	AT45BR3214B-C1
廠商：	ATMEL CORP
元件分類：	存儲(chǔ)器
英文描述：	32-MEGABIT DATAFLASH + 4-MEGABIT SRAM STACK MEMORY
中文描述：	SPECIALTY MEMORY CIRCUIT, PBGA62
封裝：	12 X 8 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, PLASTIC, CBGA-62
文件頁數(shù)：	11/40頁
文件大小：	488K
代理商：	AT45BR3214B-C1

AT45BR3214B

3356B–DFLASH–10/04

WRITE PROTECT:

If the WP pin is held low, the first 256 pages of the main memory

cannot be reprogrammed. The only way to reprogram the first 256 pages is to first drive

the protect pin high and then use the program commands previously mentioned. If this

pin and feature are not utilized it is recommended that the WP pin be driven high

externally.

RESET:

A low state on the reset pin (RESET) will terminate the operation in progress

and reset the internal state machine to an idle state. The device will remain in the reset

condition as long as a low level is present on the RESET pin. Normal operation can

resume once the RESET pin is brought back to a high level.

The device incorporates an internal power-on reset circuit, so there are no restrictions

on the RESET pin during power-on sequences. If this pin and feature are not utilized it is

recommended that the RESET pin be driven high externally.

READY/BUSY:

This open drain output pin will be driven low when the device is busy in

an internally self-timed operation. This pin, which is normally in a high state (through

a 1 k

external pull-up resistor), will be pulled low during programming operations, com-

pare operations, and during page-to-buffer transfers.

The busy status indicates that the Flash memory array and one of the buffers cannot be

accessed; read and write operations to the other buffer can still be performed.

Power-on/Reset State

When power is first applied to the device, or when recovering from a reset condition, the

device will default to SPI Mode 3. In addition, the SO pin will be in a high-impedance

state, and a high-to-low transition on the CS pin will be required to start a valid instruc-

tion. The SPI mode will be automatically selected on every falling edge of CS by

sampling the inactive clock state. After power is applied and Vcc is at the minimum

datasheet value, the system should wait 20 ms before an operational mode is started.

Table 1.

Read Commands

Command

SCK Mode

Opcode

Continuous Array Read