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參數(shù)資料
| 型號： | AT43USB326-AU |
| 廠商： | Atmel Corp. |
| 英文描述： | Multimedia USB Keyboard Controller with Embedded Hub |
| 中文描述： | 多媒體USB鍵盤控制器的嵌入式集線器 |
| 文件頁數(shù)： | 29/102頁 |
| 文件大小： | 511K |
| 代理商： | AT43USB326-AU |
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29
AT43USB326
3313D–USB–04/06
USB Endpoint
Interrupt Sources
An assertion or activation of one or more bits in the endpoint's Control and Status Register
triggers the endpoint interrupts. These triggers are different for control and non-control end-
points as described in the table below. Please refer to the Control and Status Register for
more information.
USB Interrupt Status Register – UISR
Bit 7 – SOF INT: Start of Frame Interrupt
This bit is asserted after the USB hardware receives a valid SOF packet.
Bit 6 – EOF2 INT: EOF2 Interrupt
This bit is asserted 10 clocks before the expected start of a frame.
Bit 5, 4 – Res: Reserved Bits
These bits are reserved and always read as zero.
Bit 3 – HEP0 INT: Hub Endpoint 0 Interrupt
Bit 2 – FEP2 INT: Function Endpoint 2 Interrupt
Bit 1 – FEP1 INT: Function Endpoint 1 Interrupt
Bit 0 – FEP0 INT: Function Endpoint 0 Interrupt
The hub and function interrupt bits will be set by the hardware whenever the following bits in
the corresponding endpoint's Control and Status Register are modified by the USB hardware:
1.
RX OUT Packet is set (control and OUT endpoints)
2.
TX Packet Ready is cleared AND TX Complete is set (control and IN endpoints)
3.
RX SETUP is set (control endpoints only)
4.
TX Complete is set
Table 9.
USB Endpoint Interrupt Sources
Bit
Endpoint type
RX_OUT_PACKET
CONTROL, OUT
TX_COMPLETE
CONTROL, IN
STALL_SENT
CONTROL, IN
RX_SETUP
CONTROL
Bit
7
6
5
4
3
2
1
0
$1FF7
SOF INT
EOF2 INT
–
–
HEP0 INT
FE2 INT
FE1 INT
FE0 INT
UISR
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
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