參數(shù)資料
型號: AT43USB325E-AU
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: Multimedia USB Keyboard Controller with Embedded Hub
中文描述: 8-BIT, 12 MHz, RISC MICROCONTROLLER, PQFP64
封裝: 1.40 MM HEIGHT, GREEN, PLASTIC, MS-026ACB, LQFP-64
文件頁數(shù): 27/109頁
文件大小: 643K
代理商: AT43USB325E-AU
27
3355C–USB–4/05
AT43USB325
Bits 5..0 – Res: Reserved Bits
These bits are reserved bits in the AT43USB325 and always read as zero.
4.9.2
General Interrupt Flag Register – GIFR
Bit 7 – INTF1: External Interrupt Flag1
When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-
bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at
address $004. The flag is cleared when the interrupt routine is executed. Alternatively, the flag
can be cleared by writing a logical one to it.
Bit 6 – INTF0: Interrupt Flag0 (Suspend/Resume Interrupt Flag)
When an event on the INT0 (that is, a USB event-related interrupt) triggers an interrupt request,
INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU
will jump to the interrupt vector at address $002. The flag is cleared when the interrupt routine is
executed. Alternatively, the flag can be cleared by writing a logical one to it.
Bits 5..0 – Res: Reserved Bits
These bits are reserved bits in the AT43USB325 and always read as zero.
4.9.3
Timer/Counter Interrupt Mask Register – TIMSK
Bit 7 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is
executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the
Timer/Counter Interrupt Flag Register (TIFR).
Bit 6 – OCE1A: Timer/Counter1 Output CompareA Match Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector
$004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is
set in the TIFR.
Bit 5 – OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector
Bit
7
6
5
4
3
2
1
0
$3A ($5A)
INTF1
INT F0
GIFR
Read/Write
R/W
R/W
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
$39 ($59)
TOIE1
OCIE1A
OCIE1NB
TICIE1
TOIE0
TIMSK
Read/Write
R/W
R/W
R/W
R
R/W
R
R/W
R
Initial Value
0
0
0
0
0
0
0
0
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