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參數(shù)資料
| 型號： | AT43101 |
| 廠商： | ATMEL CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCMCIA Card Memory Interface Circuit with 256 Bytes of Internal Attribute Memory EEPROM |
| 中文描述： | PCMCIA BUS CONTROLLER, PQFP64 |
| 封裝： | 1.20 MM HEIGHT, TQFP-64 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大小： | 103K |
| 代理商： | AT43101 |
INTERNAL DATA BUS: ID[15:0]
AT43101"A"
MEMORY DEVICE
D[15:0]
MEMORY DEVICE
MEMORY DEVICE
MEMORY DEVICE
MEMORY DEVICE
MEMORY DEVICE
OE*
CE* WE*
AT43101"B"
DATA
DATA
DATA
DATA
DATA
DATA
A[8:0]
A[24:9]
ICE[7:0]*
IWEH*
IOEH*
IOEL*
IWEL*
OE*
CE* WE*
OE*
CE* WE*
OE*
CE* WE*
OE*
CE* WE*
OE*
CE* WE*
WP
IWP*
WE*
REG*
A0
SGL/DBL*
CE1*
CE2*
OE*
WE*
R/B*
IR*
REG*
IA[24:9]
IA[8:1]
DEC[2:0]
SEL[1:0]
RESET
RESET
OE*
CE1*
CE2*
WPATT
IR/B*
System Block Diagram
Operation
The AT43101 is used in pairs to implement PCMCIA
Release 2.1 compatible memory cards as shown in the sys-
tem block diagram and in the internal chip block diagrams.
Both PCMCIA signals and memory devices connect directly
to the AT43101 with no additional components required. The
AT43101 acts as a data and address buffer and address and
control signal decoder for both an external memory array and
an internal 256x8 E2PROM which contains the Card Infor-
mation Structure.
The memory card is mapped into the Common Memory Ad-
dress Space of PCMCIA according to the address signals
connected to the DEC[2:0], SEL[1:0], and SGL/DBL* inputs.
In a typical configuration, SGL/DBL* and SEL[1:0] are tied
high or left floating since they are pulled up internally. Then
DEC[2:0] function as direct inputs to the address/chip enable
decoder.
For example, A[25:23] are connected to DEC[2:0] and
IA[22:1] are connected to A[21:0] of sixteen 4 Mbyte devices.
Note that A0 is used in conjunction with CE1* and CE2* to
decode the data access and is not used as a common
memory address. A[25:23] then determine which ICE[7:0]
line is active.
Mixed memory size applications can use SGL/DBL* pulled
low to enable a mixed mode decoding. This then enables
either DEC[2:0] or SEL[1:0] as inputs to the address/chip
enable decoder based on the state of SEL[1:0].
For example, the common memory space contains eight
1 Mbyte SRAM devices and six 4 Mbyte Flash devices.
A[22:21] are connected to DEC[1:0] (DEC[2] is a don’t care)
and A[24:23] are connected to SEL[1:0]. Then IA[22:1] are
used to connect to A[19:0] of the SRAM and A[21:0] of the
Flash devices. ICE[3:0]* are connected to the four SRAM
banks and ICE[7:5] to the three Flash banks. The SRAM is
then memory mapped to the lower 4 M words of addressing
and the Flash to the next 12 M words. All addressing is con-
tiguous. Notice that ICE4* can not be used with this decoding
scheme.
4
AT43101
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| AT43301-AU | Low-cost USB Hub Controller |
| AT43301-SC | Low-cost USB Hub Controller |
| AT43301-SU | Low-cost USB Hub Controller |
| AT43301-AC | Low-cost USB Hub Controller |
| AT43301 | USB HUB CONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT431A-KDR | 制造商: 功能描述:ADJUSTABLE PRECISION SHUNT REGULATORS 制造商:undefined 功能描述:ADJUSTABLE PRECISION SHUNT REGULATORS |
| AT431C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Low-Voltage Adjustable Precision Shunt Regulator |
| AT431-GRE | 制造商:AIMTRON 制造商全稱:AIMTRON 功能描述:1.24V low-Voltage Adjustable Precision Shunt Regulator |
| AT431LA-KDR | 制造商: 功能描述:Adjustable Precision Shunt Regulator 制造商:undefined 功能描述:Adjustable Precision Shunt Regulator |
| AT431UN | 制造商:AIMTRON 制造商全稱:AIMTRON 功能描述:1.24V low-Voltage Adjustable Precision Shunt Regulator |
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