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參數(shù)資料
| 型號(hào)： | AT43101 |
| 廠商： | ATMEL CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCMCIA Card Memory Interface Circuit with 256 Bytes of Internal Attribute Memory EEPROM |
| 中文描述： | PCMCIA BUS CONTROLLER, PQFP64 |
| 封裝： | 1.20 MM HEIGHT, TQFP-64 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大小： | 103K |
| 代理商： | AT43101 |
Symbol
Parameter
Min
Max
Notes
tia(A)
Delay to IA[24:0], from A[24:0]
0 ns
30 ns
tda(A)
Data access time, from A[8:0] to D[7:0]
250 ns
3
ten(CE)
Output enable time from CE*
5 ns
36 ns
1
ten(OE)
Output enable time from OE*
5 ns
36 ns
ten(REG)
Output enable time from REG*
36 ns
2
tdis(CE)
Output disable time from CE*
58 ns
1
tdis(OE)
Output disable time from OE*
58 ns
tdis(REG)
Output disable time from REG*
58 ns
tioel(A0)
Delay to IOEL*, IOEH* assertion from A0
28 ns
tioel(CE)
Delay to IOEL*, IOEH* assertion from CE*
28 ns
1
tioel(OE)
Delay to IOEL*, IOEH* assertion from OE*
25 ns
tioel(REG)
Delay to IOEL*, IOEH* assertion from REG*
28 ns
2
tioeh(A0)
Delay to IOEL*, IOEH* de-assertion from A0
28 ns
tioeh(CE)
Delay to IOEL*, IOEH* de-assertion from CE*
28 ns
1
tioeh(OE)
Delay to IOEL*, IOEH* de-assertion from OE*
25 ns
tioeh(REG)
Delay to IOEL*, IOEH* de-assertion from REG*
28 ns
2
tv(A)
Delay to data change, from change of address
0 ns
td(ID)
Delay from ID[15:0] to D[15:0]
27 ns
tice(A)
Delay to ICE[7:0]* from DEC[2:0], SEL[1:0], SGL/DBL*
38 ns
4
tice(REG)
Delay to ICE[7:0]* from REG*
38 ns
4
tice(CE)
Delay to ICE[7:0]* from CE1*, CE2*
30 ns
4
Ten (reset)
Chip active enable time from reset
50 ns
5
Tdis (reset)
Chip active disable time from reset
50 ns
5
AC Read Characteristics
Notes:
1. Either or both of CE1*, CE2* assert according to function truth table.
2. REG* asserted only for Attribute Memory read.
3. tda(A) applies to Attribute Memory read. Access time for Common Memory
read is derived from tia(A), td(ID), and external device access time.
4. Symmetrical for assertion and de-assertion. Also applies to write cycles.
5. Not shown in timing diagram.
V
DD
0V
AC MEASUREMENT LEVEL
t
R1
t
<5 ns, test load capacitance is
50pf
≥
VDD/2
Input Test Waveforms and Measurement Level
10
AT43101
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| AT43301-AU | Low-cost USB Hub Controller |
| AT43301-SC | Low-cost USB Hub Controller |
| AT43301-SU | Low-cost USB Hub Controller |
| AT43301-AC | Low-cost USB Hub Controller |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT431A-KDR | 制造商: 功能描述:ADJUSTABLE PRECISION SHUNT REGULATORS 制造商:undefined 功能描述:ADJUSTABLE PRECISION SHUNT REGULATORS |
| AT431C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Low-Voltage Adjustable Precision Shunt Regulator |
| AT431-GRE | 制造商:AIMTRON 制造商全稱:AIMTRON 功能描述:1.24V low-Voltage Adjustable Precision Shunt Regulator |
| AT431LA-KDR | 制造商: 功能描述:Adjustable Precision Shunt Regulator 制造商:undefined 功能描述:Adjustable Precision Shunt Regulator |
| AT431UN | 制造商:AIMTRON 制造商全稱:AIMTRON 功能描述:1.24V low-Voltage Adjustable Precision Shunt Regulator |
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