參數(shù)資料
型號(hào)： AT42QT1110-MZ
廠商： ATMEL CORP
元件分類： 速度傳感器和接近開關(guān)
英文描述： PROXIMITY SENSOR-CAPACITIVE, 0-5V, SQUARE, SURFACE MOUNT
封裝： 5 X 5 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-220VHHD-2, QFN-32
文件頁(yè)數(shù)： 40/46頁(yè)
文件大?。?/td> 657K
代理商： AT42QT1110-MZ
47
4519 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
VSS
VDD
IAP4
(P40–P43)
IAP6
(P60–P63)
OP4A
(P40–P43)
OP6A
(P60–P63)
TABAD
Q13
Q21 Q20
Q22
TADAB
Q12 Q11 Q10
0
1
4
8
01
1
8
10
Q13
0
1
Q13
8
2
TALA
Q13
Q23
TAQ2
TQ2A
TAQ1
TQ1A
ADF
(1)
P60/AIN0
P40/AIN4
P41/AIN5
P42/AIN6
P43/AIN7
3
1
0
10
P61/AIN1
P62/AIN2
P63/AIN3
4
Q31 Q30
Q32
Q33
TAQ3
TQ3A
4
DA converter
(Note 1)
Register A (4)
Register B (4)
DAC
operation
signal
Comparator
8-channel
multi-plexed
analog
switch
Instruction clock
A-D control circuit
Successive comparison
register (AD) (10)
A-D
interrupt
Comparator register (8)
Notes 1: This switch is turned ON only when A-D converter is operating and generates the comparison voltage.
2: Writing/reading data to the comparator register is possible only in the comparator mode (Q13=1).
The value of the comparator register is retained even when the mode is switched to the A-D conversion
mode (Q13=0) because it is separated from the successive comparison register (AD). Also, the resolution
in the comparator mode is 8 bits because the comparator register consists of 8 bits.
(Note 2)
11
Q31, Q30
10
01
00
0
1
Q32
Ring oscillator
clock
A-D conversion clock
(ADCK)
Division circuit
Divided by 48
Divided by 24
Divided by 12
Divided by 6
A-D CONVERTER (Comparator)
The 4519 Group has a built-in A-D conversion circuit that performs
conversion by 10-bit successive comparison method. Table 11
shows the characteristics of this A-D converter. This A-D converter
can also be used as an 8-bit comparator to compare analog volt-
ages input from the analog input pin with preset values.
Table 11 A-D converter characteristics
Characteristics
Successive comparison method
10 bits
Linearity error: ±2LSB (2.7 V
≤ VDD ≤ 5.5V)
Non-linearity error: ±0.9LSB (2.2 V
≤ VDD ≤ 5.5V)
31
s (f(XIN) = 6 MHz, STCK = f(XIN) (XIN
through-mode), ADCK = INSTCK/6)
8
Parameter
Conversion format
Resolution
Relative accuracy
Conversion speed
Analog input pin
Fig. 35 A-D conversion circuit structure
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