參數(shù)資料
型號: AT32UC3L064-AUR
廠商: Atmel
文件頁數(shù): 91/174頁
文件大?。?/td> 0K
描述: IC MCU AVR32 64K FLASH 48TQFP
產品培訓模塊: AVR® UC3 Introduction
標準包裝: 1
系列: AVR®32 UC3 L
核心處理器: AVR
芯體尺寸: 32-位
速度: 50MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 9x12b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 剪切帶 (CT)
配用: ATSTK600-RC34-ND - STK600 ROUTING CARD AVR
其它名稱: AT32UC3L064-AURCT
42
32099I–01/2012
AT32UC3L016/32/64
7.3
Block Diagram
Figure 7-1.
PDCA Block Diagram
7.4
Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
7.4.1
Power Management
If the CPU enters a sleep mode that disables the PDCA clocks, the PDCA will stop functioning
and resume operation after the system wakes up from sleep mode.
7.4.2
Clocks
The PDCA has two bus clocks connected: One High Speed Bus clock (CLK_PDCA_HSB) and
one Peripheral Bus clock (CLK_PDCA_PB). These clocks are generated by the Power Man-
ager. Both clocks are enabled at reset, and can be disabled in the Power Manager. It is
recommended to disable the PDCA before disabling the clocks, to avoid freezing the PDCA in
an undefined state.
7.4.3
Interrupts
The PDCA interrupt request lines are connected to the interrupt controller. Using the PDCA
interrupts requires the interrupt controller to be programmed first.
HSB to PB
Bridge
Peripheral DMA
Controller
(PDCA)
Peripheral
0
High Speed
Bus Matrix
Handshake Interfaces
Per
ip
her
al
Bus
IRQ
HSB
Interrupt
Controller
Peripheral
1
Peripheral
2
Peripheral
(n-1)
...
Memory
HSB
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