參數(shù)資料
型號: AT32UC3L064-AUR
廠商: Atmel
文件頁數(shù): 19/174頁
文件大?。?/td> 0K
描述: IC MCU AVR32 64K FLASH 48TQFP
產(chǎn)品培訓(xùn)模塊: AVR® UC3 Introduction
標(biāo)準(zhǔn)包裝: 1
系列: AVR®32 UC3 L
核心處理器: AVR
芯體尺寸: 32-位
速度: 50MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 9x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 剪切帶 (CT)
配用: ATSTK600-RC34-ND - STK600 ROUTING CARD AVR
其它名稱: AT32UC3L064-AURCT
115
32099I–01/2012
AT32UC3L016/32/64
9.6.5
Status Register
Name:
SR
Access Type:
Read-only
Offset:
0x10
Reset Value:
0x00000400
IDLE
This bit is cleared when a read or write operation to the SAU channel is started.
This bit is set when the operation is completed and no SAU bus operations are pending.
SEN: SAU Setup Mode Enable
This bit is cleared when the SAU exits setup mode.
This bit is set when the SAU enters setup mode.
EN: SAU Enabled
This bit is cleared when the SAU is disabled.
This bit is set when the SAU is enabled.
RTRADR: RTR Address Error
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set if, in the configuration phase, an RTR was written with an illegal address, i.e. the upper 16 bits in the address were
different from 0xFFFC, 0xFFFD, 0xFFFE or 0xFFFF.
MBERROR: Master Interface Bus Error
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set if a channel access generated a transfer on the master interface that received a bus error response from the
addressed slave.
URES: Unlock Register Error Status
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set if an attempt was made to unlock a channel by writing to the Unlock Register while one or more error bits were set
in SR. The unlock operation was aborted.
URKEY: Unlock Register Key Error
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set if the Unlock Register was attempted written with an invalid key.
URREAD: Unlock Register Read
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set if the Unlock Register was read.
31
30
29
28
27
26
25
24
--------
23
22
21
20
19
18
17
16
--------
15
14
13
12
11
10
9
8
-----
IDLE
SEN
EN
7654
3210
RTRADR
MBERROR
URES
URKEY
URREAD
CAU
CAS
EXP
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