參數(shù)資料
型號： AT32UC3C0512CAU-ALUT
廠商： Atmel
文件頁數(shù)： 40/110頁
文件大?。?/td> 0K
描述： IC MCU AVR32 512K FLASH 144LQFP
產(chǎn)品培訓模塊： AVR® UC3 Introduction
標準包裝： 300
系列： AVR®32 UC3 C Audio
核心處理器： AVR
芯體尺寸： 32-位
速度： 66MHz
連通性： CAN，EBI/EMI，以太網(wǎng)，I²C，IrDA，LIN，SPI，UART/USART，USB
外圍設備： 欠壓檢測/復位，DMA，I²S，POR，PWM，WDT
輸入/輸出數(shù)： 123
程序存儲器容量： 512KB（512K x 8）
程序存儲器類型： 閃存
RAM 容量： 64K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x12b，D/A 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 160-LQFP
包裝： 托盤
35
32117DS–AVR-01/12
AT32UC3C
relative to EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384
bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset),
not (EVBA + event_handler_offset), so EVBA and exception code segments must be set up
appropriately. The same mechanisms are used to service all different types of events, including
interrupt requests, yielding a uniform event handling scheme.
An interrupt controller does the priority handling of the interrupts and provides the autovector off-
set to the CPU.
4.5.1
System Stack Issues
Event handling in AVR32UC uses the system stack pointed to by the system stack pointer,
SP_SYS, for pushing and popping R8-R12, LR, status register, and return address. Since event
code may be timing-critical, SP_SYS should point to memory addresses in the IRAM section,
since the timing of accesses to this memory section is both fast and deterministic.
The user must also make sure that the system stack is large enough so that any event is able to
push the required registers to stack. If the system stack is full, and an event occurs, the system
will enter an UNDEFINED state.
4.5.2
Exceptions and Interrupt Requests
When an event other than scall or debug request is received by the core, the following actions
are performed atomically:
1.
The pending event will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM, and
GM bits in the Status Register are used to mask different events. Not all events can be
masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit, and
Bus Error) can not be masked. When an event is accepted, hardware automatically
sets the mask bits corresponding to all sources with equal or lower priority. This inhibits
acceptance of other events of the same or lower priority, except for the critical events
listed above. Software may choose to clear some or all of these bits after saving the
necessary state if other priority schemes are desired. It is the event source’s respons-
ability to ensure that their events are left pending until accepted by the CPU.
2.
When a request is accepted, the Status Register and Program Counter of the current
context is stored to the system stack. If the event is an INT0, INT1, INT2, or INT3, reg-
isters R8-R12 and LR are also automatically stored to stack. Storing the Status
Register ensures that the core is returned to the previous execution mode when the
current event handling is completed. When exceptions occur, both the EM and GM bits
are set, and the application may manually enable nested exceptions if desired by clear-
ing the appropriate bit. Each exception handler has a dedicated handler address, and
this address uniquely identifies the exception source.
3.
The Mode bits are set to reflect the priority of the accepted event, and the correct regis-
ter file bank is selected. The address of the event handler, as shown in Table 4-4 on
page 38, is loaded into the Program Counter.
The execution of the event handler routine then continues from the effective address calculated.
The rete instruction signals the end of the event. When encountered, the Return Status Register
and Return Address Register are popped from the system stack and restored to the Status Reg-
ister and Program Counter. If the rete instruction returns from INT0, INT1, INT2, or INT3,
registers R8-R12 and LR are also popped from the system stack. The restored Status Register
contains information allowing the core to resume operation in the previous execution mode. This
concludes the event handling.
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AT32UC3C064C-ALUT 功能描述:32位微控制器 - MCU UC3C 64K FLASH 16K SRAM RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT
AT32UC3C1128C-AUR 功能描述:32位微控制器 - MCU UC3C 128K FLASH 32K SRAM RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT
AT32UC3C1128C-AUT 功能描述:32位微控制器 - MCU UC3C 128K FLASH 32K SRAM RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT
AT32UC3C1256C-AUR 功能描述:32位微控制器 - MCU UC3C 256K FLASH 64K SRAM RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT
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