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參數(shù)資料
| 型號： | AT28HC256E-70JJ |
| 廠商： | ATMEL CORP |
| 元件分類： | PROM |
| 英文描述： | 32K X 8 EEPROM 5V, 70 ns, PQCC32 |
| 封裝： | PLASTIC, MS-016AE, LCC-32 |
| 文件頁數(shù)： | 19/25頁 |
| 文件大小： | 607K |
| 代理商： | AT28HC256E-70JJ |
3
0007L–PEEPR–03/08
AT28HC256
3.
Block Diagram
4.
Device Operation
4.1
Read
The AT28HC256 is accessed like a Static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state when either CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention in their system.
4.2
Byte Write
A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a
write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last.
The data is latched by the first rising edge of CE or WE. Once a byte write has been started it
will automatically time itself to completion. Once a programming operation has been initiated
and for the duration of t
WC, a read operation will effectively be a polling operation.
4.3
Page Write
The page write operation of the AT28HC256 allows 1 to 64 bytes of data to be written into the
device during a single internal programming period. A page write operation is initiated in the
same manner as a byte write; the first byte written can then be followed by 1 to 63 additional
bytes. Each successive byte must be written within 150 s (t
BLC) of the previous byte. If the
t
BLC limit is exceeded the AT28C256 will cease accepting data and commence the internal
programming operation. All bytes during a page write operation must reside on the same page
as defined by the state of the A6 - A14 inputs. That is, for each WE high to low transition dur-
ing the page write operation, A6 - A14 must be the same.
The A0 to A5 inputs are used to specify which bytes within the page are to be written. The
bytes may be loaded in any order and may be altered within the same load period. Only bytes
which are specified for writing will be written; unnecessary cycling of other bytes within the
page does not occur.
4.4
DATA Polling
The AT28HC256 features DATA Polling to indicate the end of a write cycle. During a byte or
page write cycle an attempted read of the last byte written will result in the complement of the
written data to be presented on I/O7. Once the write cycle has been completed, true data is
valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime
during the write cycle.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT28HC256E-70JU | 功能描述:電可擦除可編程只讀存儲器 256K 70ns RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| AT28HC256E-70JU-T | 功能描述:IC EEPROM 256KBIT 70NS 32PLCC 制造商:microchip technology 系列:- 包裝:剪切帶（CT） 零件狀態(tài):在售 存儲器類型:非易失 存儲器格式:EEPROM 技術(shù):EEPROM 存儲容量:256Kb （32K x 8） 寫周期時間 - 字，頁:10ms 訪問時間:70ns 存儲器接口:并聯(lián) 電壓 - 電源:4.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C（TC） 安裝類型:表面貼裝 封裝/外殼:32-LCC（J 形引線） 供應商器件封裝:32-PLCC（11.43x13.97） 標準包裝:1 |
| AT28HC256E-70PC | 功能描述:電可擦除可編程只讀存儲器 256K HI-ENDURANCE SDP - 70NS COM TEMP RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| AT28HC256E-70PI | 功能描述:電可擦除可編程只讀存儲器 256K HI-ENDURANCE SDP - 70NS IND TEMP RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| AT28HC256E-70SC | 功能描述:電可擦除可編程只讀存儲器 256K HI-ENDURANCE SDP - 70NS COM TEMP RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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