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參數(shù)資料
| 型號： | AT27RW1024 |
| 廠商： | Atmel Corp. |
| 英文描述： | 1-megabit Rewriteable PROM(1M位可重復(fù)寫的PROM) |
| 中文描述： | 1兆位可重寫胎膜早破（100萬位可重復(fù)寫的可編程） |
| 文件頁數(shù)： | 2/11頁 |
| 文件大小： | 215K |
| 代理商： | AT27RW1024 |
AT27RW1024
2
The x16 organization makes this part ideal for high-
performance 16- and 32-bit DSP and microprocessor
systems. The AT27RW1024 is pin-compatible with Atmel’s
AT49F1024/1025 and AT27C1024. In read mode, the
AT27RW1024 typically consumes 15 mA. Standby mode
supply current is typically less than 10 μA. Reprogramming
the AT27RW1024 is performed by erasing the entire chip
and then programming on a word-by-word basis. The
program and erase functions are performed with V
CC
= 5V
and V
PP
= 12V. Programming time is 20 μs per word typi-
cal. 100 program and erase cycles are guaranteed.
Block Diagram
Device Operation
READ:
When CE and OE are low and WE is high, the data
stored at the memory location determined by the address
pins is asserted on the outputs. The outputs are put in the
high impedance state whenever CE or OE is high. This
dual-line control gives designers flexibility in preventing bus
contention.
CHIP ERASE:
The chip erase will erase all words to an
FFFFH. The chip erase command is a six bus cycle opera-
tion. The address (5555H) is latched on the falling edge of
the sixth cycle while the 10H data input is latched on the
rising edge of WE. The chip erase starts after the rising
edge of WE of the sixth cycle. Please see “Chip Erase
Cycle Waveforms” on page 7. The chip erase operation is
internally controlled; it will automatically time to completion.
After a chip erase, the device will return to the read mode.
Chip erase requires V
CC
= 5V and V
PP
= 12V.
WORD PROGRAMMING:
Once the memory array is
erased, the device is programmed (to a logical “0”) on a
word-by-word basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can
convert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified t
BP
cycle
time. Programming requires V
PP
= 12V and V
CC
= 5V.
PRODUCT IDENTIFICATION:
The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
HARDWARE DATA PROTECTION:
Hardware features
protect against inadvertent programs to the AT27RW1024
in the following ways: (a) V
CC
sense: if V
CC
is below 3.8V
(typical), the program function is inhibited. (b) Program
inhibit: holding any one of OE low, CE high or WE high
inhibits program cycles. (c) Noise filter: Pulses of less than
15 ns (typical) on the WE or CE inputs will not initiate a
program cycle.
OE, CE, AND WE
LOGIC
Y DECODER
X DECODER
INPUT/OUTPUT
BUFFERS
DATA LATCH
Y-GATING
MAIN MEMORY
(64K WORDS)
OE
WE
CE
ADDRESS
INPUTS
VCC
GND
DATA INPUTS/OUTPUTS
I/O15 - I/O0
16
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