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參數(shù)資料
| 型號： | AT24C128-10TU-2.7 |
| 廠商： | ATMEL CORP |
| 元件分類： | DRAM |
| 英文描述： | Two-wire Serial EEPROMs |
| 中文描述： | 16K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封裝： | 4.40 MM, GREEN, PLASTIC, MO-153AA, TSSOP-8 |
| 文件頁數(shù)： | 10/23頁 |
| 文件大?。?/td> | 388K |
| 代理商： | AT24C128-10TU-2.7 |
10
AT24C128/256
0670S–SEEPR–5/06
Write
Operations
BYTE WRITE:
A write operation requires two 8-bit data word addresses following the device
address word and acknowledgment. Upon receipt of this address, the EEPROM will again
respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit
data word, the EEPROM will output a zero. The addressing device, such as a microcontroller,
then must terminate the write sequence with a stop condition. At this time the EEPROM enters
an internally-timed write cycle, t
WR
, to the nonvolatile memory. All inputs are disabled during
this write cycle and the EEPROM will not respond until the write is complete (see Figure 8 on
page 11).
PAGE WRITE:
The 128K/256K EEPROM is capable of 64-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not send a
stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up to 63 more data words. The
EEPROM will respond with a zero after each data word received. The microcontroller must ter-
minate the page write sequence with a stop condition (see Figure 9 on page 12).
The data word address lower 6 bits are internally incremented following the receipt of each
data word. The higher data word address bits are not incremented, retaining the memory page
row location. When the word address, internally generated, reaches the page boundary, the
following byte is placed at the beginning of the same page. If more than 64 data words are
transmitted to the EEPROM, the data word address will “roll over” and previous data will be
overwritten. The address “roll over” during write is from the last byte of the current page to the
first byte of the same page.
ACKNOWLEDGE POLLING:
Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond
with a zero, allowing the read or write sequence to continue.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT24C128-10UC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| AT24C128-10UC-1.8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| AT24C128-10UC-2.7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| AT24C128-10UI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| AT24C128-10UI-1.8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
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