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參數(shù)資料
| 型號： | AT17LV128-10SI |
| 廠商： | ATMEL CORP |
| 元件分類： | DRAM |
| 英文描述： | FPGA Configuration E2PROM |
| 中文描述： | 128K X 1 CONFIGURATION MEMORY, PDSO20 |
| 封裝： | 0.300 INCH, PLASTIC, MS-013AC, SOIC-20 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大小： | 149K |
| 代理商： | AT17LV128-10SI |
AT17 Series
7
AC Characteristics for AT17C256
V
CC
= 5V
±
5% Commercial / V
CC
= 5V
±
10% Ind./Mil.
Symbol
Description
Commercial
Industrial/Military
Units
Min
Max
Min
Max
T
OE
T
CE
T
CAC
T
OH
T
DF
T
LC
T
HC
T
SCE
T
HCE
T
HOE
F
MAX
(2)
OE to Data Delay
25
25
ns
(2)
CE to Data Delay
45
45
ns
(2)
CLK to Data Delay
50
55
ns
(2)
Data Hold From CE, OE, or CLK
0
0
ns
(3)
CE or OE to Data Float Delay
50
50
ns
CLK Low Time
20
20
ns
CLK High Time
20
20
ns
CE Setup Time to CLK (to guarantee proper counting)
35
40
ns
CE Hold Time to CLk (to guarantee proper counting)
0
0
ns
OE High Time (guarantees counter is reset)
20
20
ns
MAX Input Clock Frequency
12.5
12.5
MHz
AC Characteristics for AT17C256 When Cascading
V
CC
= 5V
±
5% Commercial / V
CC
= 5V
±
10% Ind./Mil.
Notes:
1. Preliminary specifications for military operating range only.
2. AC test load = 50 pf.
3. Float delays are measured with 5 pF AC loads. Transition is measured
±
200 mV from steady state active levels.
Symbol
Description
Commercial
Industrial/Military
Units
Min
Max
Min
Max
T
CDF
T
OCK
T
OCE
T
OOE
(3)
CLK to Data Float Delay
50
50
ns
(2)
CLK to CEO Delay
35
40
ns
(2)
CE to CEO Delay
35
35
ns
(2)
RESET/OE to CEO Delay
30
35
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT17C128-10JI | FPGA Configuration E2PROM |
| AT17C128-10PC | RSD Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 05V; Power: 1W; 1kVDC and 3kVDC Isolation Options; Approved for Medical Applications; Suitable for Automated Assembly; 8, 10 and 12 pin Pinning Style Options; Optional Continuous Short Circuit Protected; Efficiency to 85% |
| AT17C128-10PI | FPGA Configuration E2PROM |
| AT17C128-10SC | FPGA Configuration E2PROM |
| AT17C128-10SI | FPGA Configuration E2PROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17LV128-10SI SL383 | 制造商:Atmel Corporation 功能描述:EEPROM SERL-2WIRE 128KBIT 128K X 1 3.3V/5V 20SOIC - Tape and Reel |
| AT17LV128-10TQC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV128-10TQI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV128A | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV128A-10BJC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
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