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參數(shù)資料
| 型號(hào)： | AT17LV128-10SI |
| 廠商： | ATMEL CORP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | FPGA Configuration E2PROM |
| 中文描述： | 128K X 1 CONFIGURATION MEMORY, PDSO20 |
| 封裝： | 0.300 INCH, PLASTIC, MS-013AC, SOIC-20 |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大小： | 149K |
| 代理商： | AT17LV128-10SI |
AT17 Series
4
FPGA Master Serial Mode Summary
The I/O and logic functions of the FPGA and their associ-
ated interconnections are established by a configuration
program. The program is loaded either automatically upon
power up, or on command, depending on the state of the
three FPGA mode pins. In Master Mode, the FPGA auto-
matically loads the configuration program from an external
memory. The Serial Configuration EEPROM has been
designed for compatibility with the Master Serial Mode.
Cascading Serial Configuration
EEPROMs
(AT17C/LV128 and AT17C/LV256)
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories, cas-
caded Configurators provide additional memory (17C/
LV128 and 17C/LV256 only).
After the last bit from the first Configurator is read, the next
clock signal to the Configurator asserts its CEO output Low
and disables its DATA line. The second Configurator recog-
nizes the Low level on its CE input and enables its DATA
output.
Figure 1.
Condition 1 Connection
After configuration is complete, the address counters of all
cascaded Configurators are reset if the reset signal drives
the RESET/OE on each Configurator Active.
If the address counters are not to be reset upon comple-
tion, then the RESET/OE inputs can be tied to ground. For
more details, please reference the AT17C Series Program-
ming Guide.
Programming Mode
The programming mode is entered by bringing SER_EN
Low. In this mode the chip can be programmed by the 2-
wire interface. The programming is done at V
CC
supply
only. Programming super voltages are generated inside the
chip. See the Programming Specification for Atmel's Con-
figuration Memories Application Note for further informa-
tion. The AT17C Series parts are read/write at 5V nominal.
The AT17LV parts are read/write at 3.0V nominal.
AT17C/LVXXX Reset Polarity
The AT17C/LVXXX lets the user choose the reset polarity
as either RESET/OE or RESET/OE.
Standby Mode
The AT17C/LVXXX enters a low-power standby mode
whenever CE is asserted High. In this mode, the Configura-
tor consumes less than 1.0 mA of current. The output
remains in a high impedance state regardless of the state
of the OE input.
Operating Conditions
Symbol
Description
AT17CXXX
AT17LVXXX
Units
Min/Max
Min/Max
V
CC
Commercial
Supply voltage relative to GND
-0
°
C to +70
°
C
4.75/5.25
3.0/3.6
V
Industrial
Supply voltage relative to GND
-40
°
C to +85C
°
4.5/5.5
3.0/3.6
V
Military
Supply voltage relative to GND
-55
°
C to +125C
4.5/5.5
3.0/3.6
V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT17C128-10JI | FPGA Configuration E2PROM |
| AT17C128-10PC | RSD Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 05V; Power: 1W; 1kVDC and 3kVDC Isolation Options; Approved for Medical Applications; Suitable for Automated Assembly; 8, 10 and 12 pin Pinning Style Options; Optional Continuous Short Circuit Protected; Efficiency to 85% |
| AT17C128-10PI | FPGA Configuration E2PROM |
| AT17C128-10SC | FPGA Configuration E2PROM |
| AT17C128-10SI | FPGA Configuration E2PROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17LV128-10SI SL383 | 制造商:Atmel Corporation 功能描述:EEPROM SERL-2WIRE 128KBIT 128K X 1 3.3V/5V 20SOIC - Tape and Reel |
| AT17LV128-10TQC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV128-10TQI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV128A | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV128A-10BJC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
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