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參數(shù)資料
| 型號： | AT17LV020 |
| 廠商： | Atmel Corp. |
| 英文描述： | 2M bit FPGA Configuration EEPROM Memory(2M位 FPGA配置EEPROM存儲器) |
| 中文描述： | 200萬位FPGA配置存儲器（200萬位的FPGA配置的EEPROM存儲器） |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 204K |
| 代理商： | AT17LV020 |
AT17C/LV020
3
Figure 1.
Condition 2 Connection
Notes:
1. Use of the READY pin is optional.
2. Reset polarity must be set to active Low.
Condition 2
The FPGA CON pin drives only the CE input of the AT17
Series Configurator, while the OE input is driven by the
FPGA INIT pin (Figure 1). This connection works under all
normal circumstances, even when the user aborts a config-
uration before CON has gone High. A Low level on the
RESET/OE
(1)
input – during FPGA reset – clears the Con-
figurator’s internal address pointer, so that the
reconfiguration starts at the beginning.
Note:
1. For this condition, the reset polarity of the EEPROM
must be set active Low.
The AT17 Series Configurator does not require an inverter
for either condition since the RESET polarity is
programmable.
Cascading Serial Configuration
EEPROMs
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories, cas-
caded Configurators provide additional memory.
As the last bit from the first Configurator is read, the clock
signal to the Configurator asserts its CEO output Low and
disables its DATA line driver. The second Configurator
recognizes the Low level on its CE input and enables its
DATA output.
After configuration is complete, the address counters of all
cascaded Configurators are reset if the RESET/OE on
each Configurator is driven to its active (default High) level.
If the address counters are not to be reset upon comple-
tion, then the RESET/OE inputs can be tied to its inactive
(default Low) level. For more details on programming the
EEPROM’s reset polarity, please reference “Programming
Specification for Atmel’s FPGA Configuration EEPROMs”.
AT17 Series Reset Polarity
The AT17 Series Configurator allows the user to program
the reset polarity as either RESET/OE or RESET/OE. This
feature is supported by industry standard programmer
algorithms. For more details on programming the
EEPROM’s reset polarity, please reference the “Program-
ming Specification for Atmel’s FPGA Configuration
EEPROMs” application note.
Programming Mode
The programming mode is entered by bringing SER_EN
Low. In this mode the chip can be programmed by the 2-
wire serial bus. The programming is done at VCC supply
only. Programming super voltages are generated inside the
chip. See the “Programming Specification for Atmel's
FPGA Configuration EEPROMs” application note for fur-
ther information. The AT17C parts are read/write at 5V
nominal. The AT17LV parts are read/write at 3.3V nominal.
Standby Mode
The AT17C/LV020 enters a low-power standby mode
whenever CE is asserted High. In this mode, the Configura-
tor consumes less than 0.5 mA of current at 5.0 volts with
CMOS level inputs. The output remains in a high imped-
ance state regardless of the state of the OE input.
RESET
M2
M1
M0
D<0>
CCLK
CON
INIT
RESET
AT40K
DATA
CLK
CE
RESET/OE
SER_EN
READY
AT17C/LV020
VCC
GND
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| AT17C128-10JC | FPGA Configuration E2PROM |
| AT17LV65-10JC | FPGA Configuration E2PROM |
| AT17LV65-10JI | FPGA Configuration E2PROM |
| AT17LV65-10PC | FPGA Configuration E2PROM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17LV020-10JC | 功能描述:FPGA-配置存儲器 2M bit FPGA RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17LV020-10JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EEPROM |
| AT17LV020A | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV020A-10JC | 功能描述:FPGA-配置存儲器 Serial EEPROM RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17LV020A10JI | 制造商:Atmel Corporation 功能描述: |
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