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參數資料
| 型號： | AT17LV020 |
| 廠商： | Atmel Corp. |
| 英文描述： | 2M bit FPGA Configuration EEPROM Memory(2M位 FPGA配置EEPROM存儲器) |
| 中文描述： | 200萬位FPGA配置存儲器（200萬位的FPGA配置的EEPROM存儲器） |
| 文件頁數： | 2/12頁 |
| 文件大小： | 204K |
| 代理商： | AT17LV020 |
AT17C/LV020
2
Block Diagram
FPGA Master Serial Mode Summary
The I/O and logic functions of the FPGA and their associ-
ated interconnections are established by a configuration
program. The program is loaded either automatically upon
power-up, or on command, depending on the state of the
FPGA mode pins. In Master Mode, the FPGA automatically
loads the configuration program from an external memory.
The AT17 Serial Configuration EEPROM has been
designed for compatibility with the Master Serial Mode.
This document discusses the AT40K FPGA interface. For
more details or AT6K FPGA applications, please reference
“AT40K Series Configuration” or “AT6000 Series Configu-
ration” application notes.
Controlling the High-density AT17
Series Serial EEPROMs During
Configuration
Most connections between the FPGA device and the AT17
Serial EEPROM are simple and self-explanatory:
The DATA output of the AT17 Series Configurator drives
DIN of the FPGA devices.
The master FPGA CCLK output drives the CLK input of
the AT17 Series Configurator.
The CEO output of any AT17C/LV020 drives the CE input
of the next AT17C/LV020 in a cascade chain of
EEPROMs.
SER_EN must be connected to VCC, (except during
ISP).
The READY pin is available as an open-collector indicator
of the device’s RESET status; it is driven Low while the
device is in its POWER-ON RESET cycle and released
(tri-stated) when the cycle is complete.
There are two different ways to use the inputs CE and OE.
Condition 1
The simplest connection is to have the FPGA CON pin
drive both CE and RESET/OE
(1)
in parallel. Due to its sim-
plicity, however, this method will fail if the FPGA receives
an external reset condition during the configuration cycle. If
a system reset is applied to the FPGA, it will abort the origi-
nal configuration and then reset itself for a new
configuration, as intended. Of course, the AT17 Series
Configurator does not see the external reset signal and will
not reset its internal address counters and, consequently,
will remain out of sync with the FPGA for the remainder of
the configuration cycle.
Note:
1. For this condition, the reset polarity of the EEPROM
must be set active High.
CEO (A2)
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| AT17C128-10JC | FPGA Configuration E2PROM |
| AT17LV65-10JC | FPGA Configuration E2PROM |
| AT17LV65-10JI | FPGA Configuration E2PROM |
| AT17LV65-10PC | FPGA Configuration E2PROM |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AT17LV020-10JC | 功能描述:FPGA-配置存儲器 2M bit FPGA RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17LV020-10JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EEPROM |
| AT17LV020A | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV020A-10JC | 功能描述:FPGA-配置存儲器 Serial EEPROM RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17LV020A10JI | 制造商:Atmel Corporation 功能描述: |
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