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參數(shù)資料
| 型號： | AT17LV010-10DP-MQ |
| 廠商： | ATMEL CORP |
| 元件分類： | DRAM |
| 英文描述： | Space FPGA Configuration EEPROM |
| 中文描述： | 1M X 1 CONFIGURATION MEMORY, DFP28 |
| 封裝： | 0.400 INCH, DFP-28 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大小： | 179K |
| 代理商： | AT17LV010-10DP-MQ |
5
A717LV010-10DP
4265B–AERO–06/04
FPGA Master Serial
Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configura-
tion program. The program is loaded either automatically upon power-up, or on
command, depending on the state of the FPGA mode pins. In Master mode, the FPGA
automatically loads the configuration program from an external memory. The AT17LV
Serial Configuration EEPROM has been designed for compatibility with the Master
Serial mode.
This document discusses the Atmel AT40KEL applications.
Control of
Configuration
Most connections between the FPGA device and the AT17LV Serial EEPROM are sim-
ple and self-explanatory.
The DATA output of the AT17LV010-10DP configurator drives DIN of the FPGA
devices.
The master FPGA CCLK output drives the CLK input of the AT17LV010-10DP
configurator.
The CEO output of any AT17LV010-10DP configurator drives the CE input of the
next configurator in a cascaded chain of EEPROMs.
SER_EN must be connected to V
CC
(except during ISP).
The READY pin is available as an open-collector indicator of the device’s reset
status; it is driven Low while the device is in its power-on reset cycle and released
(tri-stated) when the cycle is complete.
Cascading Serial
Configuration
EEPROMs
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configu-
ration memories, cascaded configurators provide additional memory.
After the last bit from the first configurator is read, the clock signal to the configurator
asserts its CEO output Low and disables its DATA line driver. The second configurator
recognizes the Low level on its CE input and enables its DATA output.
After configuration is complete, the address counters of all cascaded configurators are
reset if the RESET/OE on each configurator is driven to its active (Low) level.
If the address counters are not to be reset upon completion, then the RESET/OE input
can be tied to its inactive (High) level.
Reset PAT17LV010-
10DPolarity
The AT17LV010-10DP configurator allows the user to program the reset polarity as
either RESET/OE or RESET/OE. This feature is supported by industry-standard pro-
grammer algorithms.
Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can
be programmed by the Two-Wire serial bus. The programming is done at V
CC
supply
only. Programming super voltages are generated inside the chip.
Standby Mode
The AT17LV010-10DP configurator enter a low-power standby mode whenever CE is
asserted High. In this mode, the AT17LV010-10DP configurator consumes less than
100 μA of current at 3.3V. The output remains in a high-impedance state regardless of
the state of the OE input.
相關PDF資料 |
PDF描述 |
|---|---|
| AT17LV010-10DP-E | Space FPGA Configuration EEPROM |
| AT17LV010-10DP-M | Space FPGA Configuration EEPROM |
| AT17LV010-10DP-SV | Space FPGA Configuration EEPROM |
| AT17LV256A | 256K FPGA Configuration EEPROM Memory(256K 現(xiàn)場可編程門陣列（FPGA）配置EEPROM存儲器) |
| AT17LV512 | 512K FPGA Configuration EEPROM Memory(512K 現(xiàn)場可編程（FPGA）配置EEPROM存儲器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AT17LV010-10DP-SV | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Space FPGA Configuration EEPROM |
| AT17LV010-10JC | 功能描述:FPGA-配置存儲器 CONFIG SERIAL EEPROM 1M 3.3V - 10MHZ RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17LV010-10JC SL383 | 制造商:Atmel Corporation 功能描述:EEPROM SERL-2WIRE 1MBIT 1M X 1 3.3V/5V 20PLCC - Tape and Reel |
| AT17LV010-10JC SL735 | 制造商:Atmel Corporation 功能描述:FPGA CONFIG SERIAL EEPROM, 1M, |
| AT17LV01010JI | 制造商:ATMEL 功能描述:* |
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