- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381398 > AT17LV010-10DP-MQ (ATMEL CORP) Space FPGA Configuration EEPROM PDF資料下載
參數(shù)資料
| 型號： | AT17LV010-10DP-MQ |
| 廠商： | ATMEL CORP |
| 元件分類： | DRAM |
| 英文描述： | Space FPGA Configuration EEPROM |
| 中文描述： | 1M X 1 CONFIGURATION MEMORY, DFP28 |
| 封裝： | 0.400 INCH, DFP-28 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 179K |
| 代理商： | AT17LV010-10DP-MQ |
4
A717LV010-10DP
4265B–AERO–06/04
Pin Description
DATA
Tri-state DATA output for configuration. Open-collector bi-directional pin for
programming.
CLK
Clock input. Used to increment the internal address and bit counter for reading and
programming.
WP1
WRITE PROTECT (1). Used to protect portions of memory during programming. Dis-
abled by default due to internal pull-down resistor. This input pin is not used during
FPGA loading operations.
RESET/OE
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low
level on RESET/OE resets both the address and bit counters. A High level (with CE
Low) enables the data output driver. The logic polarity of this input is programmable as
either RESET/OE or RESET/OE. For most applications, RESET should be programmed
active Low. This document describes the pin as RESET/OE.
WP2
WRITE PROTECT (2). Used to protect portions of memory during programming. Dis-
abled by default due to internal pull-down resistor. This input pin is not used during
FPGA loading operations.
CE
Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the
address counter and enables the data output driver. A High level on CE disables both
the address and bit counters and forces the device into a low-power standby mode.
Note that this pin will
not
enable/disable the device in the Two-Wire Serial Programming
mode (SER_EN Low).
GND
Ground pin. A 0.2 μF decoupling capacitor between V
CC
and GND is recommended.
CEO
Chip Enable Output (active Low). This output goes Low when the address counter has
reached its maximum value. In a daisy chain of AT17LV010-10DP devices, the CEO pin
of one device must be connected to the CE input of the next device in the chain. It will
stay Low as long as CE is Low and OE is High. It will then follow CE until OE goes Low;
thereafter, CEO will stay High until the entire EEPROM is read again.
A2
Device selection input, A2. This is used to enable (or select) the device during program-
ming (i.e., when SER_EN is Low). A2 has an internal pull-down resistor.
READY
Open collector reset state indicator. Driven Low during power-up reset, released when
power-up is complete. It is recommended to use a 4.7 k
pull-up resistor when this pin
is used.
SER_EN
Serial enable must be held High during FPGA loading operations. Bringing SER_EN
Low enables the Two-Wire Serial Programming Mode. For non-ISP applications,
SER_EN should be tied to V
CC
.
V
CC
3.3V (±0.3V).
相關PDF資料 |
PDF描述 |
|---|---|
| AT17LV010-10DP-E | Space FPGA Configuration EEPROM |
| AT17LV010-10DP-M | Space FPGA Configuration EEPROM |
| AT17LV010-10DP-SV | Space FPGA Configuration EEPROM |
| AT17LV256A | 256K FPGA Configuration EEPROM Memory(256K 現(xiàn)場可編程門陣列（FPGA）配置EEPROM存儲器) |
| AT17LV512 | 512K FPGA Configuration EEPROM Memory(512K 現(xiàn)場可編程（FPGA）配置EEPROM存儲器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AT17LV010-10DP-SV | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Space FPGA Configuration EEPROM |
| AT17LV010-10JC | 功能描述:FPGA-配置存儲器 CONFIG SERIAL EEPROM 1M 3.3V - 10MHZ RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17LV010-10JC SL383 | 制造商:Atmel Corporation 功能描述:EEPROM SERL-2WIRE 1MBIT 1M X 1 3.3V/5V 20PLCC - Tape and Reel |
| AT17LV010-10JC SL735 | 制造商:Atmel Corporation 功能描述:FPGA CONFIG SERIAL EEPROM, 1M, |
| AT17LV01010JI | 制造商:ATMEL 功能描述:* |
發(fā)布緊急采購，3分鐘左右您將得到回復。