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參數(shù)資料
| 型號(hào)： | AT17C512 |
| 廠商： | Atmel Corp. |
| 英文描述： | FPGA Configuration E2PROM Memory |
| 中文描述： | FPGA配置E2PROM的記憶 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 113K |
| 代理商： | AT17C512 |
AT17C/LV512/010
3
Pin Configurations
20
PLCC
Name
I/O
Description
2
DATA
I/O
Three-state DATA output for reading. Input/Output pin for programming.
4
CLK
I
Clock input. Used to increment the internal address and bit counter for reading and
programming.
5
WP1
I
WRITE PROTECT (1). Used to protect portions of memory during programming. See
programming guide for details.
6
RESET/OE
I
RESET/Output Enable input (when SER_EN is High). A Low level on both the CE and
RESET/OE inputs enables the data output driver. A High level on RESET/OE resets both the
address and bit counters. The logic polarity of this input is programmable as either RESET/OE
or RESET/OE. This document describes the pin as RESET/OE.
7
WP2
I
WRITE PROTECT (2). Used to protect portions of memory during programming. See
programming guide for details.
8
CE
I
Chip Enable input. Used for device selection. A Low level on both CE and OE enables the data
output driver. A High level on CE disables both the address and bit counters and forces the
device into a low power mode. Note this pin will not enable/disable the device in 2-wire Serial
Programming mode (i.e., when SER_EN is Low).
10
GND
Ground pin.
14
CEO
O
Chip Enable Out output. This signal is asserted Low on the clock cycle following the last bit
read from the memory. It will stay Low as long as CE and OE are both Low. It will then follow
CE until OE goes High. Thereafter, CEO will stay High until the entire PROM is read again and
senses the status of RESET polarity.
A2
I
Device selection input, A2. This is used to enable (or select) the device during programming,
when SER_EN is Low (see Programming Guide for more details)
15
READY
O
Open collector reset state indicator. Driven Low during power-up reset, released when power-
up is complete. (Recommend a 4.7K
Pull-up on this pin if used).
17
SER_EN
I
Serial enable is normally high during FPGA loading operations. Bringing SER_EN Low,
enables the two wire serial interface mode for programming.
20
V
CC
+3.3V/+5V power supply pin.
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
*NOTICE:
Stresses beyond those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the
device. These are stress ratings only, and functional
operation of the device at these or any other condi-
tions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Rat-
ings conditions for extended periods of time may
affect device reliability.
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground............................-0.1V to V
CC
+ 0.5V
Supply Voltage (V
CC
).........................................-0.5V to +7.0V
Maximum Soldering Temp. (10 s @ 1/16 in.)..................260°C
ESD (R
ZAP
= 1.5K, C
ZAP
= 100 pF)............................... 2000V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT17C512-10JC | FPGA Configuration E2PROM Memory |
| AT17C512-10JI | FPGA Configuration E2PROM Memory |
| AT17LV010A-10BJI | FPGA Configuration EEPROM Memory |
| AT17C010-10JC | FPGA Configuration E2PROM Memory |
| AT17C010-10JI | FPGA Configuration E2PROM Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17C512-10CC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EEPROM |
| AT17C512-10CI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EEPROM |
| AT17C512-10JC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration E2PROM Memory |
| AT17C512-10JI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration E2PROM Memory |
| AT17C512-10PC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EEPROM |
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