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參數(shù)資料
| 型號(hào)： | AT17C512-10JI |
| 廠(chǎng)商： | ATMEL CORP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | FPGA Configuration E2PROM Memory |
| 中文描述： | 512K X 1 CONFIGURATION MEMORY, PQCC20 |
| 封裝： | PLASTIC, LCC-20 |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大?。?/td> | 113K |
| 代理商： | AT17C512-10JI |
1
Features
E
2
Programmable 524,288 x 1 and 1,048,576 x 1 bit Serial Memories Designed To Store
Configuration Programs For Field Programmable Gate Arrays (FPGA)
Simple Interface to SRAM FPGAs
Compatible With Atmel AT6000, AT40K FPGAs, Altera EPF8K, EPF10K,
EPF6K FPGAs, ORCA FPGAs, Xilinx XC3000, XC4000, XC5200 FPGAs, Motorola
MPA1000 FPGAs
Cascadable To Support Additional Configurations or Future Higher-density Arrays
Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available In PLCC Package (Pin Compatable across Product Family)
In-System Programmable Via 2-Wire Bus
Emulation of 24CXX Serial EPROMs
Available in 3.3V
±
10% LV and 5V Versions
System Friendly READY Pin
Description
The AT17C512/010 and AT17LV512/010 (high-density AT17 Series) FPGA Configu-
ration EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration
memory for Field Programmable Gate Arrays. The high-density AT17 Series is pack-
aged in the popular 20-pin PLCC. The high-density AT17 Series family uses a simple
serial-access procedure to configure one or more FPGA devices. The high-density
AT17 Series organization supplies enough memory to configure one or multiple
smaller FPGAs. The user can select the polarity of the reset function by programming
one EEPROM byte. The devices also support a write protection mode and a system
friendly READY pin, which signifies a “good” power level to the device and can be
used to ensure reliable system power-up.
The high-density AT17 Series can be programmed with industry-standard program-
mers, and the Atmel ATDH2200 Programming board.
FPGA
Configuration
E
2
PROM
Memory
512K and 1M
AT17C512
AT17LV512
AT17C010
AT17LV010
Rev. 0944A-A–12/97
Pin Configurations
20-Pin PLCC
RESET/OE
CE
4
9
5
10
6
11
7
12
8
13
18
17
16
15
14
3
2
1
20
19
CLK
D
A
T
A
V
C
C
N
C
N
N
C
READY
NC
WP2
NC
WP1
N
C
N
C
N
C
N
C
SER_EN
CEO
G
N
D
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT17LV010A-10BJI | FPGA Configuration EEPROM Memory |
| AT17C010-10JC | FPGA Configuration E2PROM Memory |
| AT17C010-10JI | FPGA Configuration E2PROM Memory |
| AT17LV010-10SI | FPGA Configuration EEPROM Memory |
| AT17LV010-10TQC | FPGA Configuration EEPROM Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17C512-10PC | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Configuration EEPROM |
| AT17C512-10PI | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Configuration EEPROM |
| AT17C512A | 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17C512A-10JC | 制造商:Atmel Corporation 功能描述: |
| AT17C512A-10JI | 制造商:Atmel Corporation 功能描述: |
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