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參數(shù)資料
| 型號： | AT17C020A |
| 廠商： | Atmel Corp. |
| 元件分類： | FPGA |
| 英文描述： | FPGA Configuration EEPROM Memory |
| 中文描述： | FPGA配置EEPROM存儲器 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大小： | 242K |
| 代理商： | AT17C020A |
11
AT17C/LV002A
2280B
–
08/01
Notes:
1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels.
Notes:
1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels.
AC Characteristics for AT17LV002A
V
CC
= 3.3V ± 5% Commercial/V
CC
= 3.3V ± 5% Industry/Military
Symbol
Description
Commercial
Industrial/Military
(1)
Units
Min
Max
Min
Max
T
OE
(2)
OE to Data Delay
50
55
ns
T
CE
(2)
nCS to Data Delay
55
60
ns
T
CAC
(2)
DCLK to Data Delay
60
65
ns
T
OH
Data Hold From nCS, OE or DCLK
0.0
0
ns
T
DF
(3)
nCS or OE to Data Float Delay
50
50
ns
T
LC
DCLK Low Time Slave Mode
25
25
ns
T
HC
DCLK High Time Slave Mode
25
25
ns
T
SCE
nCS Setup Time to DCLK (to guarantee proper counting)
35
40
ns
T
HCE
nCS Hold Time from DCLK (to guarantee proper
counting)
0
0
ns
T
LOE
OE Low Time (guarantees counter is reset)
20
20
ns
F
MAX
Maximum Input Clock Frequency Slave Mode
15
10
MHz
T
LC
DCLK Low Time Master Mode
30
300
30
300
ns
T
HC
DCLK High Time Master Mode
30
300
30
300
ns
AC Characteristics for AT17LV002A When Cascading
V
CC
= 3.3V ± 5% Commercial/V
CC
= 3.3V ± 5% Industry/Military
Symbol
Description
Commercial
Industrial/Military
(1)
Units
Min
Max
Min
Max
T
CDF
(3)
DCLK to Data Float Delay
50
50
ns
T
OCK
(2)
DCLK to nCASC Delay
50
55
ns
T
OCE
(2)
nCS to nCASC Delay
35
40
ns
T
OOE
(2)
OE to nCASC Delay
35
35
ns
F
MAX
Maximum Input Clock Frequency Slave Mode
12.0
10
MHz
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