參數(shù)資料
型號(hào)： AT17C002A-10QI
廠商： ATMEL CORP
元件分類： DRAM
英文描述： FPGA Configuration EEPROM Memory
中文描述： 2M X 1 CONFIGURATION MEMORY, PQFP32
封裝： 1 MM HEIGHT, PLASTIC, TQFP-32
文件頁(yè)數(shù)： 6/14頁(yè)
文件大小： 242K
代理商： AT17C002A-10QI
6
AT17C/LV002A
2280B
–
08/01
Pin Configurations
20
PLCC
Pin
32
TQFP
Pin
Name
I/O
Description
2
31
DATA
I/O
Three-state data output for configuration. Open-collector bi-directional pin for programming.
4
2
DCLK
I/O
Clock output or clock input. Rising edges on DCLK increment the internal address counter
and present the next bit of data to the DATA pin. The counter is incremented only if the OE
input is held High, the nCS input is held Low, and all configuration data has not been
transferred to the target device (otherwise, as the master device, the DCLK pin drives Low).
5
4
WP1
I
WRITE PROTECT (1). Used to protect portions of memory during programming. Disabled by
default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations. See the
“
Programming Specification for Atmel
’
s Configuration EEPROMs
”
application note for more details.
8
7
OE
I
Output enable (active High) and reset (active Low) when SER_EN is High. A Low logic level
resets the address counter. A High logic level (with nCS Low) enables DATA and permits the
address counter to count. In the mode, if this pin is Low (reset), the internal oscillator
becomes inactive and DCLK drives Low. The logic polarity of this input is programmable and
must be programmed active High (RESET active Low) by the user during programming for
Altera applications.
9
10
nCS
I
Chip select input (active Low). A Low input (with OE High) allows DCLK to increment the
address counter and enables DATA to drive out. If the AT17A Series is reset with nCS Low,
the device initializes as the first (and master) device in a daisy chain. If the AT17A Series is
reset with nCS High, the device initializes as a subsequent AT17A Series device in the chain.
10
12
GND
Ground pin. A 0.2 μF decoupling capacitor should be placed between the VCC and GND
pins.
12
15
nCASC
O
Cascade select output (active Low). This output goes Low when the address counter has
reached its maximum value. In a daisy chain of AT17A Series devices, the nCASC pin of one
device is usually connected to the nCS input pin of the next device in the chain, which
permits DCLK from the master configurator to clock data from a subsequent AT17A Series
device in the chain.
A2
I
Device selection input, A2. This is used to enable (or select) the device during programming,
(i.e., when SER_EN is Low; please refer to the
“
Programming Specification for Atmel
’
s
Configuration EEPROMs
”
application note for more details.)
15
20
READY
O
Open collector reset state indicator. Driven Low during power-up reset, released (tri-stated)
when power-up is complete. (Recommend a 4.7 k
pull-up on this pin if used.)
18
23
SER_EN
I
Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low
enables the 2-wire serial programming mode.
20
27
VCC
+3.3V/+5V power supply pin
相關(guān)PDF資料
PDF描述
AT17C020 2M bit FPGA Configuration EEPROM Memory(2M位 FPGA配置EEPROM存儲(chǔ)器)
AT17LV020 2M bit FPGA Configuration EEPROM Memory(2M位 FPGA配置EEPROM存儲(chǔ)器)
AT17C128-10JC FPGA Configuration E2PROM
AT17LV65-10JC FPGA Configuration E2PROM
AT17LV65-10JI FPGA Configuration E2PROM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AT17C010 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration E2PROM Memory
AT17C010-10 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration E2PROM Memory
AT17C010-10CC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EEPROM
AT17C010-10CI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EEPROM
AT17C010-10JC 功能描述:FPGA-配置存儲(chǔ)器 1M 15MHz 5V RoHS:否 制造商:Altera Corporation 存儲(chǔ)類型:Flash 存儲(chǔ)容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-20
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