
ASM5P23S09A
ASM5P23S05A
August 2003
rev 2.0
3.3V
‘SpreadTrak’ Zero Delay Buffer
6 of 16
Notice: The information in this document is subject to change without notice.
Electrical Characteristics for ASM5P23S05A and ASM5P23S09A - Commercial Temperature Devices
Parameter
Description
Test Conditions
Min
Max
Unit
V
IL
Input LOW Voltage
5
Input HIGH Voltage
5
0.8
V
V
IH
2.0
V
I
IL
Input LOW Current
V
IN
= 0V
50.0
μA
I
IH
Input HIGH Current
Output LOW Voltage
6
V
IN
= V
DD
100.0
μA
V
OL
I
OL
= 8mA (-1)
I
OH
= 12mA (-1H)
0.4
V
V
OH
Output HIGH Voltage
6
I
OL
= -8mA (-1)
I
OH
= -12mA (-1H)
2.4
V
I
DD
Supply Current
Unloaded outputs at 66.67 MHz,
SEL inputs at V
DD
TBD
mA
Notes:
5. REF input has a threshold voltage of VDD/2
6. Parameter is guaranteed by design and characterization. Not 100% tested in production
7. S1 / S2 inputs are CMOS, TTL compatible inputs
–
The input must toggle somewhere between 0.8 and 2.0. We guarantee the limits of 0.8 and 2.0, but can't guarantee anything tighter than
that. As Vdd moves higher the toggle point will move higher, but will always stay below 2.0V. As Vdd moves lower, the toggle point will
move lower, but always stay higher than 0.8V. What the 2.0V MIN Vih specification means is that you put 2.0V or a higher voltage into the
device, and you will have a logic HIGH. If you put 0.8V or a lower voltage into the device, you will have a logic LOW ( Vil spec = 0.8V max).
It will toggle someplace in between 0.8V and 2.0V, but we don't guarantee exactly where, and the exact point will change depending upon
conditions. Characterization shows we toggle at 1.1V and 1.5V (showing a little hysteresis), everything is perfect. We meet spec, plus have
~ 300mV noise immunity on the low end and ~500mV noise immunity on the high side. Under nominal conditions, with no hysteresis, most
devices will toggle at about 1.5V for both high and low.
Switching Characteristics for ASM5P23S05A-1 and ASM5P23S09A-1 -
Commercial Temperature Devices
7
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
1/t
1
Output Frequency
30-pF load
10-pF load
10
10
100
133.3 3
MHz
Duty Cycle
6
= (t
2
/ t
1
) * 100
Output Rise Time
6
Output Fall Time
6
Output-to-output skew
6
Measured at 1.4V, F
OUT
= 66.67 MHz
40.0
50.0
60.0
%
t
3
Measured between 0.8V and 2.0V
2.50
ns
t
4
Measured between 2.0V and 0.8V
2.50
ns
t
5
All outputs equally loaded
250
ps
t
6
Delay, REF Rising Edge to
CLKOUT Rising Edge
6
Device-to-Device Skew
6
Measured at V
DD
/2
0
±350
ps
t
7
Measured at V
DD
/2 on the CLKOUT pins of the device
0
700
ps
t
J
Cycle-to-cycle jitter
6
PLL Lock Time
6
Measured at 66.67 MHz, loaded outputs
200
ps
t
LOCK
Stable power supply, valid clock presented on
REF pin
1.0
ms
Notes:
7. All parameters specified with loaded outputs.