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參數(shù)資料
| 型號(hào)： | ASM5P2305AF-1H-08-TR |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 3.3V Zero Delay Buffer |
| 中文描述： | 2305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 4.40 MM, TSSOP-8 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 398K |
| 代理商： | ASM5P2305AF-1H-08-TR |
ASM5P2309A
September 2005
ASM5P2305A
rev 1.6
3.3V Zero Delay Buffer
3 of 20
Notice: The information in this document is subject to change without notice.
CLK2
CLK3
1
2
3
5
6
7
8
ASM5P2305A
REF
CLK1
GND
VDD
CLKOUT
CLK4
4
Pin Configuration
Pin Description for ASM5P2309A
Pin #
Pin Name
Description
1
REF
2
Input reference frequency, 5V tolerant input
2
CLKA1
3
Buffered clock output, bank A
3
CLKA2
3
Buffered clock output, bank A
4
VDD
3.3V supply
5
GND
Ground
6
CLKB1
3
Buffered clock output, bank B
7
CLKB2
3
Buffered clock output, bank B
8
S2
4
Select input, bit 2
9
S1
4
Select input, bit 1
10
CLKB3
3
Buffered clock output, bank B
11
CLKB4
3
Buffered clock output, bank B
12
GND
Ground
13
VDD
3.3V supply
14
CLKA3
3
Buffered clock output, bank A
15
CLKA4
3
Buffered clock output, bank A
16
CLKOUT
3
Buffered output, internal feedback on this pin
S2
2
1
3
4
5
6
7
8
CLKA2
VDD
GND
CLKB1
CLKB2
CLKA1
REF
11
9
10
12
13
14
15
16
CLKA3
CLKA4
CLKB3
CLKB4
VDD
CLKOUT
GND
ASM5P2309A
S1
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PDF描述 |
|---|---|
| ASM5P2305AF-1H-08-TT | 3.3V Zero Delay Buffer |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5P2305AF-1H-08-TT | 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V Zero Delay Buffer |
| ASM5P2305AG-1-08-SR | 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V Zero Delay Buffer |
| ASM5P2305AG-1-08-ST | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V Zero Delay Buffer |
| ASM5P2305AG-1-08-TR | 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V Zero Delay Buffer |
| ASM5P2305AG-1-08-TT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V Zero Delay Buffer |
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