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參數(shù)資料
| 型號： | ASM5P2305AF-1H-08-TR |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 3.3V Zero Delay Buffer |
| 中文描述： | 2305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 4.40 MM, TSSOP-8 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 398K |
| 代理商： | ASM5P2305AF-1H-08-TR |
ASM5P2309A
September 2005
ASM5P2305A
rev 1.6
3.3V Zero Delay Buffer
2 of 20
Notice: The information in this document is subject to change without notice.
Select Input Decoding for ASM5P2309A
S2
S1
Clock A1 - A4
Clock B1 - B4
CLKOUT
1
Output Source
PLL
Shut-Down
0
Three-state
Driven
PLL
N
0
1
Driven
Three-state
Driven
PLL
N
1
0
Driven
Reference
Y
1
Driven
PLL
N
Notes:
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and the
output.
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero
Delay between input and output. Since the CLKOUT pin is
the internal feedback to the PLL, its relative loading can
adjust the input-output delay.
For applications requiring zero input-output delay, all
outputs, including CLKOUT, must be equally loaded. Even
if CLKOUT is not used, it must have a capacitive load equal
to that on other outputs, for obtaining zero-input-output
delay.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5P2305AF-1H-08-TT | 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V Zero Delay Buffer |
| ASM5P2305AG-1-08-SR | 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V Zero Delay Buffer |
| ASM5P2305AG-1-08-ST | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V Zero Delay Buffer |
| ASM5P2305AG-1-08-TR | 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V Zero Delay Buffer |
| ASM5P2305AG-1-08-TT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V Zero Delay Buffer |
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