- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381377 > ASM5I9775A-52-ET (ALLIANCE SEMICONDUCTOR CORP) Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 PDF資料下載
參數(shù)資料
| 型號(hào)： | ASM5I9775A-52-ET |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
| 中文描述： | 9775 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | 1 MM HEIGHT, TQFP-52 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 507K |
| 代理商： | ASM5I9775A-52-ET |
June 2005
ASM5I9775A
rev 0.3
AC Electrical Specifications
6
(VDD= 2.5V ± 5%, T
A
= –40°C to +85°C)
Parameter
Description
f
VCO
VCO Frequency
2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer
7 of 12
Notice: The information in this document is subject to change without notice.
Condition
Min
200
Typ
-
Max
400
Unit
MHz
÷4 Feedback
50
-
100
÷6 Feedback
33.3
-
66.6
÷8 Feedback
25
-
50
÷12 Feedback
16.7
-
33.3
÷16 Feedback
12.5
-
25
÷24 Feedback
8.3
-
16.7
÷32 Feedback
6.3
-
12.5
÷48 Feedback
4.2
-
8.3
f
in
Input Frequency
Bypass mode (PLL_EN = 0)
0
-
200
MHz
f
refDC
Input Duty Cycle
25
-
75
%
t
r
, t
f
TCLK Input Rise/Fall Time
0.7V to 1.7V
-
-
1.0
nS
÷2 Output
100
-
200
÷4 Output
50
-
100
÷6 Output
33.3
-
66.6
÷8 Output
25
-
50
÷12 Output
16.7
-
33.3
÷16 Output
12.5
-
25
f
MAX
Maximum Output Frequency
÷24 Output
8.3
-
16.7
MHz
DC
Output Duty Cycle
45
-
55
%
t
r
, t
f
Output Rise/Fall times
Propagation Delay
(static phase offset)
Output-to-Output Skew
0.7V to 1.8V
TCLK to FB_IN, does not
include jitter
Skew within Bank
0.1
-
1.0
nS
t
(
φ
)
-100
-
100
pS
t
sk(O)
-
-
150
pS
Banks at same frequency
-
-
150
t
sk(B)
Bank-to-Bank Skew
Banks at different frequency
-
-
225
pS
t
PLZ, HZ
Output Disable Time
-
-
10
nS
t
PZL, ZH
Output Enable Time
-
-
10
nS
VCO_SEL = 0
-
0.5 - 1.0
-
BW
PLL Closed Loop Bandwidth
(–3 dB)
VCO_SEL = 1
-
1.0 - 2.0
-
MHz
Same frequency
-
-
150
t
JIT(CC)
Cycle-to-Cycle Jitter
Multiple frequencies
-
-
300
pS
t
JIT(PER)
Period Jitter
-
-
100
pS
t
JIT(
φ
)
I/O Phase Jitter
-
-
150
pS
t
LOCK
Maximum PLL Lock Time
-
-
1
mS
Note:
6. AC characteristics apply for parallel output termination of 50
to V
TT
. Parameters are guaranteed by characterization and are not 100% tested.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9775AG-52-ER | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
| ASM5I9775AG-52-ET | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
| ASM5P2304A-1H-08-SR | 3.3 V Zero Delay Buffer |
| ASM5I2304A-1H-08-SR | 3.3 V Zero Delay Buffer |
| ASM5P2304A-2H-08-SR | 3.3 V Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9775AG-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer |
| ASM5I9775AG-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer |
| ASM5P2304A | 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V Zero Delay Buffer |
| ASM5P2304A-1-08-SR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3 V Zero Delay Buffer |
| ASM5P2304A-1-08-ST | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3 V Zero Delay Buffer |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。