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參數(shù)資料
| 型號(hào)： | ASM5I9775A-52-ET |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
| 中文描述： | 9775 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | 1 MM HEIGHT, TQFP-52 |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 507K |
| 代理商： | ASM5I9775A-52-ET |
June 2005
ASM5I9775A
rev 0.3
2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer
6 of 12
Notice: The information in this document is subject to change without notice.
DC Electrical Specifications (
VDD= 3.3V ± 5%, T
A
Parameter
Description
Condition
Min
Typ
Max
Unit
V
IL
Input Voltage, Low
LVCMOS
-
-
0.8
V
V
IH
Input Voltage, High
LVCMOS
2.0
-
VDD+0.3
V
I
OL
= 24 mA
-
-
0.55
V
OL
Output Voltage, Low
4
I
OL
= 12 mA
-
-
0.30
V
V
OH
Output Voltage, High
4
I
OH
= –24 mA
2.4
-
-
V
I
IL
Input Current, Low
5
V
IL
= VSS
-
-
-100
μA
I
IH
Input Current, High
5
V
IL
= VDD
-
-
100
μA
I
DDA
PLL Supply Current
AVDD only
-
5
10
mA
I
DDQ
Quiescent Supply Current
All VDD pins except AVDD
-
-
1
mA
Outputs loaded @ 100 MHz
-
225
-
I
DD
Dynamic Supply Current
Outputs loaded @ 200 MHz
-
290
-
mA
C
IN
Input Pin Capacitance
-
4
-
pF
Z
OUT
Output Impedance
12
15
18
DC Electrical Specifications (
VDD= 2.5V ± 5%, T
A
= –40°C to +85°C)
Parameter
Description
Condition
Min.
Typ.
Max
Unit
V
IL
Input Voltage, Low
LVCMOS
-
-
0.7
V
V
IH
Input Voltage, High
LVCMOS
1.7
-
VDD+0.3
V
V
OL
Output Voltage, Low
4
I
OL
= 15 mA
-
-
0.6
V
V
OH
Output Voltage, High
4
I
OH
= –15 mA
1.8
-
-
V
I
IL
Input Current, Low
5
V
IL
= VSS
-
-
-100
μA
I
IH
Input Current, High
5
V
IL
= VDD
-
-
100
μA
I
DDA
PLL Supply Current
AVDD only
-
5
10
mA
I
DDQ
Quiescent Supply Current
All VDD pins except AVDD
-
-
1
mA
Outputs loaded @ 100 MHz
-
135
-
I
DD
Dynamic Supply Current
Outputs loaded @ 200 MHz
-
160
-
mA
C
IN
Input Pin Capacitance
-
4
-
pF
Z
OUT
Output Impedance
14
18
22
Notes:
4. Driving one 50
parallel terminated transmission line to a termination voltage of V
TT
. Alternatively, each output drives up to two 50
series terminated
transmission lines.
5. Inputs have pull-up or pull-down resistors that affect the input current.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9775AG-52-ER | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
| ASM5I9775AG-52-ET | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
| ASM5P2304A-1H-08-SR | 3.3 V Zero Delay Buffer |
| ASM5I2304A-1H-08-SR | 3.3 V Zero Delay Buffer |
| ASM5P2304A-2H-08-SR | 3.3 V Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9775AG-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer |
| ASM5I9775AG-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer |
| ASM5P2304A | 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V Zero Delay Buffer |
| ASM5P2304A-1-08-SR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3 V Zero Delay Buffer |
| ASM5P2304A-1-08-ST | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3 V Zero Delay Buffer |
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