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參數(shù)資料
| 型號(hào)： | ASM5I9352G-32-LT |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| 中文描述： | 9352 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 1 MM HEIGHT, GREEN, LQFP-32 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 475K |
| 代理商： | ASM5I9352G-32-LT |
July 2005
rev 0.2
AC Electrical Specifications
(V
DD
= 3.3V ± 5%, T
A
= -40°C to +85°C)
1
ASM5I9352
2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer
7 of
12
Notice: The information in this document is subject to change without notice.
Parameter
f
VCO
Description
Condition
Min
200
Typ
Max
500
Unit
MHz
VCO Frequency
÷2 Feedback
100
200
÷4 Feedback
÷6 Feedback
50
33.33
125
83.33
÷8 Feedback
÷12 Feedback
Bypass mode (PLL_EN# = 1)
0.8V to 2.0V
÷2 Output
25
62.5
41.67
200
16.67
0
f
in
Input Frequency
MHz
f
refDC
Input Duty Cycle
25
100
75
%
t
r
, t
f
TCLK Input Rise/FallTime
1.0
200
nS
÷4 Output
÷6 Output
÷8 Output
50
33.33
25
125
83.33
62.5
f
MAX
Maximum Output Frequency
÷12 Output
16.67
41.67
MHz
f
MAX
< 100 MHz
f
MAX
> 100 MHz
48
44
52
56
DC
Output Duty Cycle
%
t
r
, t
f
Output Rise/Fall times
Propagation Delay
(static phase offset)
Output-to-Output Skew
0.55V to 2.4V
TCLK to FB_IN, same V
DD
,
does not include jitter
Skew within each Bank
Banks at same voltage,
same frequency
Banks at same voltage,
different frequency
Banks at different voltage
÷2 Feedback
÷4 Feedback
0.1
1.0
nS
t
(
φ
)
–100
200
pS
t
sk(O)
125
pS
175
235
t
sk(B)
Bank-to-Bank Skew
425
8
pS
t
PLZ, HZ
Output Disable Time
nS
t
PZL, ZH
Output Enable Time
10
100
275
100
nS
2
1 – 1.5
÷6 Feedback
0.6
÷8 Feedback
÷12 Feedback
0.75
0.5
150
100
BW
PLL Closed Loop Bandwidth
(-3dB)
MHz
Same frequency
Multiple frequencies
Same frequency
t
JIT(CC)
Cycle-to-Cycle Jitter
pS
t
JIT(PER)
Period Jitter
Multiple frequencies
150
1
pS
VCO < 300 MHz
VCO > 300 MHz
t
JIT(
φ
)
I/O Phase Jitter
pS
t
LOCK
Note:1
.
AC characteristics apply for parallel output termination of 50
to V
TT
. Parameters are guaranteed by characterization and are not 100% tested.
Maximum PLL Lock Time
mS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9352 | 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| ASM5I9352-32-ET | 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| ASM5I9352-32-LT | 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| ASM5I961CG-32-ET | Low Voltage Zero Delay Buffer |
| ASM5I961CG-32-LT | Low Voltage Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I961C | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961C-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961C-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961CG-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961CG-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
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