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參數(shù)資料
| 型號： | ASM5I9351-32-LT |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| 中文描述： | 9351 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 1 MM HEIGHT, LQFP-32 |
| 文件頁數(shù)： | 3/13頁 |
| 文件大?。?/td> | 522K |
| 代理商： | ASM5I9351-32-LT |
July 2005
rev 0.2
ASM5I9351
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
3 of 13
Notice: The information in this document is subject to change without notice.
Pin Configuration
1
Pin #
8
Pin Name
PECL_CLK
I/O
I, PU
Type
Analog
Description
LVPECL reference clock input
.
LVPECL reference clock input
. Weak pull-up to VDD/2.
LVCMOS/LVTTL reference clock input
Clock output bank A
Clock output bank B
Clock output bank C
9
PECL_CLK#
I, PU/PD
Analog
30
TCLK
I, PD
LVCMOS
28
QA
O
LVCMOS
26
QB
O
LVCMOS
22, 24
12, 14, 16, 18,
20
QC(1:0)
O
LVCMOS
QD(4:0)
O
LVCMOS
Clock output bank D
2
FB_IN
I, PD
LVCMOS
Feedback clock input
. Connect to an output for normal
operation. This input should be at the same voltage rail as
input reference clock. See
Table 1
.
Output enable/disable input
. See
Table 2
.
PLL enable/disable input
. See
Table 2
.
Reference select input
. See
Table 2
.
Frequency select input, Bank (A:D)
. See
Table 2
.
2.5V or 3.3V Power supply for bank B output clock
2,3
2.5V or 3.3V Power supply for bank C output clocks
2,3
2.5V or 3.3V Power supply for bank D output clocks
2,3
2.5V or 3.3V Power supply for PLL
2,3
2.5V or 3.3V Power supply for core, inputs, and bank A
output clock
Analog ground
10
OE#
I, PD
LVCMOS
31
PLL_EN
I, PU
LVCMOS
32
3, 4, 5, 6
27
23
15, 19
1
REF_SEL
SEL(A:D)
VDDQB
VDDQC
VDDQD
AVDD
I, PD
I, PD
Supply
Supply
Supply
Supply
LVCMOS
LVCMOS
VDD
VDD
VDD
VDD
11
VDD
Supply
VDD
7
13, 17, 21, 25,
29
Note: 1
PU = Internal pull-up, PD = Internal pull-down.
2. A 0.1μF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins
their high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD output
power supply pins.
AVSS
Supply
Ground
VSS
Supply
Ground
Common ground
相關PDF資料 |
PDF描述 |
|---|---|
| ASM5I9352G-32-ET | CONNECTOR ACCESSORY |
| ASM5I9352G-32-LT | 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| ASM5I9352 | 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| ASM5I9352-32-ET | 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| ASM5I9352-32-LT | 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9351G-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351G-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9352 | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| ASM5I9352-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| ASM5I9352-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
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