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參數(shù)資料
| 型號： | ASM5I2304A-2H-08-SR |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 3.3 V Zero Delay Buffer |
| 中文描述： | 2304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 0.150 INCH, SOIC-8 |
| 文件頁數(shù)： | 6/15頁 |
| 文件大小： | 300K |
| 代理商： | ASM5I2304A-2H-08-SR |
September 2005
ASM5P2304A
rev 1.4
3.3V Zero Delay Buffer
6 of 15
Notice: The information in this document is subject to change without notice.
Switching Characteristics for ASM5P2304A Commercial Temperature Devices
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
1/t
1
Output Frequency
30pF load, -1H, -2H devices
15
133
MHz
1/t
1
Output Frequency
15pF load, -1, -2 devices
15
133
MHz
Duty Cycle
5
= (t
2
/ t
1
) * 100
(-1, -2, -1H, -2H)
Measured at 1.4V, F
OUT
= 66.66MHz
30pF load
40.0
50.0
60.0
%
Duty Cycle
5
= (t
2
/ t
1
) * 100
(-1, -2,-1H, -2H)
Measured at 1.4V, F
OUT
= <50MHz
15 pF load
45.0
50.0
55.0
%
t
3
Output Rise Time
5
(-1, -2)
Measured between 0.8V and 2.0V
30pF load
2.20
nS
t
3
Output Rise Time
5
(-1, -2)
Measured between 0.8V and 2.0V
15pF load
1.50
nS
t
3
Output Rise Time
5
(-1H, -2H)
Measured between 0.8V and 2.0V
30pF load
1.50
nS
t
4
Output Fall Time
5
(-1, -2)
Measured between 2.0V and 0.8V
30pF load
2.20
nS
t
4
Output Fall Time
5
(-1, -2)
Measured between 2.0V and 0.8V
15pF load
1.50
nS
t
4
Output Fall Time
5
(-1H, -2H)
Measured between 2.0V and 0.8V
30pF load
1.25
nS
Output-to-output skew on same bank (-1, -2)
5
All outputs equally loaded
200
Output-to-output skew (-1H, -2H)
All outputs equally loaded
200
Output bank A -to- output bank B skew
(-1, -2H)
All outputs equally loaded
200
t
5
Output bank A to output Bank B skew (-2)
All outputs equally loaded
400
pS
t
6
Delay, REF Rising Edge to FBK Rising Edge
5
Measured at V
DD
/2
0
±250
pS
t
7
Device-to-Device Skew
5
Measured at V
DD
/2 on the FBK pins of the device
0
500
pS
t
8
Output Slew Rate
5
Measured between 0.8V and 2.0V using
Test Circuit #2
1
V/nS
Measured at 66.67MHz, loaded outputs,
15pF load
175
Measured at 66.67MHz, loaded outputs,
30pF load
200
t
J
Cycle-to-cycle jitter
5
(-1, -1H, -2H)
Measured at 25MHz, loaded outputs,
15pF load
100
pS
Measured at 66.67MHz, loaded outputs, 30pF load
400
t
J
Cycle-to-cycle jitter
5
(-2)
Measured at 66.67MHz, loaded outputs,
15pF load
375
pS
t
LOCK
PLL Lock Time
5
Stable power supply, valid clock presented on REF
and FBK pins
1.0
mS
Note:
5. Parameter is guaranteed by design and characterization. Not 100% tested in production.
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| ASM5P2304AF-2H-08-SR | 3.3 V Zero Delay Buffer |
| ASM5I2304AF-2H-08-SR | 3.3 V Zero Delay Buffer |
| ASM5P2304AG-2H-08-SR | 3.3 V Zero Delay Buffer |
| ASM5I2304AG-2H-08-SR | 3.3 V Zero Delay Buffer |
| ASM5P2304AG-1-08-ST | 3.3 V Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I2304A-2H-08-ST | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3 V Zero Delay Buffer |
| ASM5I2304A-5H-08-SR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3 V Zero Delay Buffer |
| ASM5I2304A-5H-08-ST | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3 V Zero Delay Buffer |
| ASM5I2304AF-1-08-SR | 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V Zero Delay Buffer |
| ASM5I2304AF-1-08-ST | 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V Zero Delay Buffer |
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