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參數(shù)資料
| 型號： | ASM5I2304A-2H-08-SR |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 3.3 V Zero Delay Buffer |
| 中文描述： | 2304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 0.150 INCH, SOIC-8 |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 300K |
| 代理商： | ASM5I2304A-2H-08-SR |
September 2005
ASM5P2304A
rev 1.4
3.3V Zero Delay Buffer
2 of 15
Notice: The information in this document is subject to change without notice.
ASM5P2304A Configurations
Device
Feedback From
Bank A Frequency
Bank B Frequency
ASM5P2304A-1
Bank A or Bank B
Reference
Reference
ASM5P2304A-1H
Bank A or Bank B
Reference
Reference
ASM5P2304A-2
Bank A
Reference
Reference /2
ASM5P2304A-2
Bank B
2 X Reference
Reference
ASM5P2304A-2H
Bank A
Reference
Reference/2
ASM5P2304A-2H
Bank B
2 X Reference
Reference
Zero Delay and Skew Control
For applications requiring zero input-output delay, all outputs must be equally loaded
.
To close the feedback loop of the ASM5P2304A, the FBK
pin can be driven from any of the four available output pins.
The output driving the FBK pin will be driving a total load of
7pF plus any additional load that it drives. The relative
loading of this output (with respect to the remaining
outputs) can adjust the input output delay. This is shown in
the above graph.
For applications requiring zero input-output delay, all
outputs including the one providing feedback should be
equally loaded. If input-output delay adjustments are
required, use the above graph to calculate loading
differences between the feedback output and remaining
outputs. For zero output-output skew, be sure to load
outputs equally.
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
0
-500
-1000
-1500
500
1000
1500
Output Load Difference: FBK Load - CLKA/CLKB Load (pF)
R
REF Input to CLKA/CLKB Delay Vs Difference in Loading between FBK pin and CLKA/CLKB pins
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5P2304AF-2H-08-SR | 3.3 V Zero Delay Buffer |
| ASM5I2304AF-2H-08-SR | 3.3 V Zero Delay Buffer |
| ASM5P2304AG-2H-08-SR | 3.3 V Zero Delay Buffer |
| ASM5I2304AG-2H-08-SR | 3.3 V Zero Delay Buffer |
| ASM5P2304AG-1-08-ST | 3.3 V Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I2304A-2H-08-ST | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3 V Zero Delay Buffer |
| ASM5I2304A-5H-08-SR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3 V Zero Delay Buffer |
| ASM5I2304A-5H-08-ST | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3 V Zero Delay Buffer |
| ASM5I2304AF-1-08-SR | 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V Zero Delay Buffer |
| ASM5I2304AF-1-08-ST | 制造商:PULSECORE 制造商全稱:PulseCore Semiconductor 功能描述:3.3V Zero Delay Buffer |
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