- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381362 > ASM2I99447 (Alliance Semiconductor Corporation) 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer PDF資料下載
參數(shù)資料
| 型號(hào)： | ASM2I99447 |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer |
| 中文描述： | 3.3V/2.5V 1:9的LVCMOS時(shí)鐘扇出緩沖器 |
| 文件頁(yè)數(shù)： | 4/14頁(yè) |
| 文件大?。?/td> | 565K |
| 代理商： | ASM2I99447 |
第1頁(yè)第2頁(yè)第3頁(yè)當(dāng)前第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)
May 2005
rev 0.3
ASM2I99447
3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
4 of 14
Table 6. AC Characteristics
(V
CC
= 3.3V ± 5%, T
A
= –40°C to +85°C)
1
Symbol
f
ref
f
max
f
P
,
REF
t
r
, t
f
t
PLH/HL
t
PLZ, HZ
t
PZL, ZH
5Characteristics
Min
0
0
1.4
1.3
Typ
Max
350
350
1.0
2
3.3
11
11
Unit
MHz
MHz
nS
nS
nS
nS
nS
Condition
0.8 to 2.0V
Input Frequency
Output Frequency
Reference Input Pulse Width
CCLK0, CCLK1 Input Rise/Fall Time
Propagation Delay CCLK0 or CCLK1 to any Q
Output Disable Time
Output Enable Time
Setup Time CCLK0 or CCLK1 to CLK_STOP
3
Hold Time CCLK0 or CCLK1 to CLK_STOP
3
Output-to-Output Skew
Device-to-Device Skew
Output Pulse Skew
4
Output Duty Cycle fQ<170
MHz
Output Rise/Fall Time
Cycle-to-cycle jitter RMS (1
σ
)
Note: 1.
AC characteristics apply for parallel output termination of 50
to V
TT
.
2. Violation of the 1.0 nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,
output duty cycle and maximum frequency specifications.
3. Setup and hold times are referenced to the falling edge of the selected clock signal input.
4. Output pulse skew is the absolute difference of the propagation delay times: | t
PLH
- t
PHL
|.
t
S
0.0
nS
t
H
1.0
nS
t
sk(O)
t
sk(PP)
150
2.0
pS
nS
t
SK(P)
DCQ
45
50
300
55
pS
%
DC
REF
= 50%
t
r
, t
f
t
JIT(CC)
0.1
1.0
nS
pS
0.55 to 2.4V
TBD
Table 7. DC Characteristics
(V
CC
= 2.5V ± 5%, TA = –40°C to +85°C)
Symbol
V
IH
V
IL
V
OH
V
OL
Z
OUT
I
IN
I
CCQ
Note: 1.The ASM2I99447 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50
parallel terminated transmission line to
a termination voltage of V
TT
. Alternatively, the device drives one 50
series terminated transmission lines per output (V
CC
=2.5V).
2. Inputs have pull-down or pull-up resistors affecting the input current.
3. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
Characteristics
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output Impedance
Input Current
2
Maximum Quiescent Supply Current
3
Min
1.7
-0.3
1.8
Typ
19
Max
V
CC
+ 0.3
0.7
0.6
±300
2.0
Unit
V
V
V
V
mA
mA
Condition
LVCMOS
LVCMOS
I
OH
=-15 mA
1
I
OL
= 15 mA
V
IN
= V
CC
or GND
All V
CC
Pins
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM2I99448G-32-ER | 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| ASM2I99448G-32-ET | 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| ASM2I99448G-32-LR | CAP CERM 470PF 500V X7R 10% 1206 |
| ASM2I99448G-32-LT | 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| ASM2I99448 | 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM2I99448 | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| ASM2I99448-32-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| ASM2I99448-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| ASM2I99448-32-LR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| ASM2I99448-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。