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參數(shù)資料
| 型號： | ASM2I99446G-32-ET |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | CONV DC-DC 120W 48VIN 1.2V SMD |
| 中文描述： | 99446 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, GREEN, TQFP-32 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大小： | 575K |
| 代理商： | ASM2I99446G-32-ET |
July 2005
rev 0.4
ASM2I99446
2.5V and 3.3V LVCMOS Clock Distribution Buffer 5 of 14
Notice: The information in this document is subject to change without notice.
Table 7: AC CHARACTERISTICS
(V
CC
= V
CCA
= V
CCB
= V
CCC
= 3.3V ±5%, T
A
= –40°C to +85°C)
1
Symbol
f
ref
Characteristics
Min
Typ
0
0
0
1.4
2.2
2.2
Max
250
2
250
2
125
1.0
3
4.45
4.2
10
10
Unit
MHz
MHz
MHz
nS
nS
nS
nS
nS
nS
Condition
FSELx=0
FSELx=1
0.8 to 2.0V
Input Frequency
f
MAX
Maximum Output Frequency
÷1 output
÷2 output
CCLK0,1 to any Q
CCLK0,1 to any Q
t
P
,
REF
t
r
, t
f
t
PLH
t
PHL
t
PLZ,
HZ
t
PZL, LZ
Reference Input Pulse Width
CCLK Input Rise/Fall Time
Propagation delay
2.8
2.8
Output Disable Time
Output Enable Time
Output-to-output Skew
Within one bank
Any output Bank, Same output divider
Any output, Any output divider
Device-to-device Skew
Output pulse skew
4
t
sk(O)
150
200
350
pS
pS
pS
t
sk(PP)
t
SK(P)
2.25
200
53
55
nS
pS
%
%
DC
Q
Output Duty Cycle
÷1 output
÷2 output
47
45
50
50
DC
REF
= 50%
DC
REF
= 25%-75%
t
r
, t
f
Output Rise/Fall Time
0.1
1.0
nS
0.55 to 2.4V
Note: 1 AC characteristics apply for parallel output termination of 50
to V
TT
2 The ASM2I99446 is functional up to an input and output clock frequency of 350MHz and is characterized up to 250MHz.
3 Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,
output duty cycle and maximum frequency specifications.
4 Output pulse skew is the absolute difference of the propagation delay times | t
pLH
- t
pHL
|.
Table 8: DC CHARACTERISTICS
(V
CC
= V
CCA
= V
CCB
= V
CCC
= 2.5V ±5%, T
A
= –40°C to +85°C)
Symbol
V
IH
V
IL
V
OH
V
OL
Z
OUT
I
IN
I
CCQ
Note: 1 The ASM2I99446 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50
parallel terminated transmission line to
a termination voltage of V
. Alternatively, the device drives up to two 50
series terminated transmission lines per output.
2 Input pull-up / pull-down resistors influence input current.
3 I
CCQ
is the DC current consumption of the device with all outputs open and the input in its default state or open.
Characteristics
Min
1.7
-0.3
1.8
Typ
17 - 20
2
Max
V
CC
+ 0.3
0.7
0.6
±200
2.0
Unit
V
V
V
V
μA
mA
Condition
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output Impedance
Input Current
2
Maximum Quiescent Supply Current
LVCMOS
LVCMOS
I
OH
=-15 mA
1
I
OL
= 15 mA
V
IN
=GND or V
IN
=V
CC
All V
CC
Pins
3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM2I99446G-32-LR | 2.5V and 3.3V LVCMOS Clock Distribution Buffer |
| ASM2I99446G-32-LT | 2.5V and 3.3V LVCMOS Clock Distribution Buffer |
| ASM2I99447 | 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer |
| ASM2I99448G-32-ER | 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| ASM2I99448G-32-ET | 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM2I99446G-32-LR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V and 3.3V LVCMOS Clock Distribution Buffer |
| ASM2I99446G-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V and 3.3V LVCMOS Clock Distribution Buffer |
| ASM2I99447 | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer |
| ASM2I99448 | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| ASM2I99448-32-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
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