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參數(shù)資料
| 型號： | ASM1232LPU-T |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | MSOP-8 |
| 文件頁數(shù)： | 12/13頁 |
| 文件大?。?/td> | 377K |
| 代理商： | ASM1232LPU-T |
ASM1232LP/LPS
Rev. 2 | Page 8 of 13 | www.onsemi.com
DC Electrical Characteristics
Unless otherwise stated, 4.5V
≤ V
CC ≤ 5.5V and over the operating temperature range of 0°C to 70°C (-40°C to +85°C. for N devices). All
Voltages are referenced to ground.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Supply Voltage
VCC
4.5
5.5
V
ST and PBRST Input High Level
VIH
2
VCC + 0.3
V
ST and PBRST Input Low Level
VIL
-0.3
0.8
V
VCC Trip Point (TOL = GND)
VCCTP
4.50
4.62
4.74
V
VCC Trip Point (TOL = VCC)
VCCTP
4.25
4.37
4.49
V
Watchdog Timeout Period
tTD
TD = GND
62.5
150
250
ms
Watchdog Timeout Period
tTD
TD = VCC
500
1200
2000
ms
Watchdog Timeout Period
tTD
TD Floating
250
610
1000
ms
Output Voltage
VOH
I=-500
μA
3
VCC - 0.5
VCC - 0.1
V
Output Current
IOH
Output = 2.4V
2
-8
-10
mA
Output Current
IOL
Output = 0.4V
10
mA
Input Leakage
IIL
1
-1.0
1.0
μA
RESET Low Level
VOL
3
0.4
V
Internal Pull-up Resistor
1
40
kΩ
Operating Current (CMOS)
ICC1
30
μA
Input Capacitance
CIN
5
pF
Output Capacitance
COUT
10
pF
PBRST Manual Reset
Minimum Low Time
tPB
PBRST = VIL
20
ms
Reset Active Time
tRST
250
610
1000
ms
ST Pulse Width
tST
4
20
ns
VCC Fail Detect to RESET or RESET
tRPD
5
8
μs
VCC Slew Rate
tF
4.75V to 4.25V
300
μs
PBRST Stable LOW to RESET and
RESET Active
tPDLY
20
ms
VCC Detect to RESET or RESET
inactive
tRPU
tRISE = 5μs
250
610
1000
ms
VCC Slew Rate
tR
4.25V to 4.75V
0
ns
Notes: 1. PBRST is internally pulled HIGH to V
CC through a nominal 40kΩ resistor.
2. RESET is an open drain output.
3. RESET remains within 0.5V of V
CC on power-down until VCC falls below 2V. RESET remains within 0.5V of ground on power-
down until V
CC falls below 2.0V.
4. Must not exceed the minimum watchdog time-out period (t
TD). The watchdog circuit cannot be disabled. To avoid a reset, ST
must be strobed.
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